Advantech iDAQ-731, User Manual

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iDAQ-731_751_763D User Manual 36
A.1 Isolated Digital Input (iDAQ-731)

Channels: 16

Input type: Sink (NPN)
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Input logic level (referenced to DICOM)
– OFF state: 0 V ~ +3 V
– ON state: +10 V ~ +40 V
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Input current draw
– OFF state: 1 mA max.
– ON state: 3 mA max.

Input protection voltage: +60 V max, -8 V min.

Response time: 100 μs max.

Debounce filter: 10 μs ~ 84 ms, software configurable

Isolation protection: 600 V
RMS

Acquisition type: Instant or buffered, software configurable

Buffered acquisition
– Sample rate: 10 kHz max., software configurable
– Internal data buffer (FIFO) size: 512 samples, each sample contains state
of all channels Interrupt
– Edge detection: Rising edge, falling edge, or both edges, software configu -
rable for each channel independently
– Pattern match detection: By port detection, each channel can be enabled
or disabled by software independently
– Frequency: 1 kHz max.
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Other feature: Latch digital input states when interrupt occurs

Timing signal output to chassis: From one of the digital input channels or dig -
ital input pattern match event, software configurable
A.2 TTL Digital Input (iDAQ-751)

Input logic level
– Logic high: 2.3 V min.
– Logic low: 1.0 V max.
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Working voltage: -0.25 V ~ 5.25 V

Input protection voltage: -0.5 V ~ +6.5 V
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Isolation protection: 60 VDC

Pull-down resistor: 50 kΩ

Response time: 5 μs max.

Debounce filter: 40 ns ~ 84 ms, software configurable

Acquisition type: Instant or buffered, software configurable

Buffered acquisition
– Sample rate: 200 kHz max., software configurable
– Internal data buffer (FIFO) size: 512 samples, each sample contains state
of all channels

Interrupt
– Edge detection: Rising edge, falling edge, or both edges, software configu -
rable for each channel independently
– Pattern match detection: By port detection, each channel can be enabled
or disabled by software independently