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iDAQ-731_751_763D User Manual

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3.6

Configuration for Buffered Digital Output

Generation

According to software configurations, buffered digital output generation can be classi

-

fied into two types:



One-buffered digital output generation



Streaming digital output generation

3.6.1

One-Buffered Digital Output Generation

For one-buffered generation, only a specified number of samples is generated. The

generation starts when a start trigger is received and automatically stops when the

specified number of samples is generated. An example of 5-sample generation is

shown in Figure 3.23.

Figure 3.23 One-buffered generation.

The start trigger can be a software command or a hardware signal. If a hardware sig

-

nal is used as the start trigger, the start of generation can be delayed for a specified

number of sample clock cycles after a start trigger is received. Figure 2-6 shows an

example of a 2-sample delay post-trigger generation. Refer to the device specifica

-

tions for possible signal sources.

Figure 3.24 One-buffered generation with delay.

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Summary of Contents for iDAQ-731

Page 1: ...User Manual iDAQ 731 iDAQ 751 iDAQ 763D Digital I O and Relay Industrial DAQ Modules ...

Page 2: ...ech assumes no liability under the terms of this warranty as a consequence of such events Because of Advantech s high quality control standards and rigorous testing most customers never need to use our repair service If an Advantech product is defective it will be repaired or replaced free of charge during the warranty period For out of warranty repairs customers will be billed according to the co...

Page 3: ...he equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Opera tion of this equipment in a residential area is likely to cause harmful interference In such cases users are required to correct the interference...

Page 4: ...terminal block x 2 Startup Manual x 1 iDAQ 751 iDAQ 751 x 1 Startup Manual x 1 iDAQ 763D iDAQ 731 x 1 20 pin terminal block x 2 Startup Manual x 1 Warning Warnings indicate conditions that if not observed can cause personal injury Caution Cautions are included to help prevent hardware damage and data losses For example Batteries are at risk of exploding if incorrectly installed Do not attempt to r...

Page 5: ...r pour liquid into an opening This may cause fire or electrical shock 13 Never open the equipment For safety reasons the equipment should be opened only by qualified service personnel 14 If any of the following occurs have the equipment checked by service person nel The power cord or plug is damaged Liquid has penetrated the equipment The equipment has been exposed to moisture The equipment is mal...

Page 6: ... Dies könnte einen Brand bzw elektrischen Schlag aus lösen 13 Öffnen Sie niemals das Gerät Das Gerät darf aus Gründen der elektrischen Sicherheit nur von authorisiertem Servicepersonal geöffnet werden 14 Wenn folgende Situationen auftreten ist das Gerät vom Stromnetz zu trennen und von einer qualifizierten Servicestelle zu überprüfen Netzkabel oder Netzstecker sind beschädigt Flüssigkeit ist in da...

Page 7: ...age To avoid electrical shock always disconnect the power from the PC chassis before manual handling Do not touch any components on the CPU card or other cards while the PC is powered on Disconnect the power before making any configuration changes A sudden rush of power after connecting a jumper or installing a card may damage sensitive electronic components ...

Page 8: ...iDAQ 731_751_763D User Manual viii ...

Page 9: ...put signal connection 10 Figure 2 4 Sink NPN type digital output signal connection 10 Figure 2 5 Source PNP type digital output signal connection 11 2 2 3 TTL Digital Input 12 Figure 2 6 Digital input signal connection 12 Figure 2 7 Digital input signal connection using a switch with inter nally pulled down 13 2 2 4 TTL Digital Output 13 Figure 2 8 Digital output signal connection 13 2 2 5 Solid s...

Page 10: ...tal Output 28 3 5 1 Static Digital Output Update 28 Figure 3 19Static digital output update 28 3 5 2 Buffered Digital Output Waveform Generation 28 Figure 3 20Buffered digital output waveform generation 28 Figure 3 21Start and stop of the digital output waveform genera tion 29 Figure 3 22Start and stop of the digital output waveform generation with delay 29 3 5 3 Digital Output Fail Safe Function ...

Page 11: ...Chapter 1 1 Start Using IDAQ 731 751 763D ...

Page 12: ...ures driver utility and accessories The iDAQ 731 iDAQ 751 and iDAQ 763D are digital I O modules The function for these models are isolated digital I O TTL I O and solid state relay SSR respec tively All of the iDAQ modules could be used in all kinds of iDAQ chassis In the following sections the detailed use instruction and functions will be described Figure 1 1 iDAQ 731 iDAQ 751 Figure 1 2 iDAQ 75...

Page 13: ... each iDAQ module follows a rule combining the Chas sisID and slot number Refer to section 3 4 for all the detailed information 1 2 3 Plug and Play Device iDAQ modules are hot swappable in iDAQ chassis The modules are recognized instantly in the software when they re plugged into the iDAQ slots the same when they are unplugged Therefore it s strongly recommended not to perform this while the syste...

Page 14: ...the Advantech Naviga tor program by accessing Start Programs Advantech Automation DAQNavi Advantech Navigator The settings could also be saved to 2 You can then view the device s already installed on your system if any on the Installed Device tree view If the software and hardware installation are com pleted you will see iDAQ modules in the Installed Devices list 1 5 Software Development Using DAQ...

Page 15: ...ge but also in remote storage By introducing the DAQNavi MCM the DAQ system could become an IoT solution ready edge device For more information please search for DAQNavi MCM on the Advantech Support Portal https www advantech com support 1 7 FPGA Code Update The FPGA can also be updated via the interface in Navigator However it isn t normal to make an FPGA update Advantech strongly suggests you to...

Page 16: ...iDAQ 731_751_763D User Manual 6 ...

Page 17: ...Chapter 2 2 Installation and Field Application ...

Page 18: ...module installation to signal wiring for the iDAQ modules Below are the steps to insert the iDAQ modules into the iDAQ chassis 1 Insert the module and follow the guide rail to the end 2 Fix the two screws tight onto the chassis Figure 2 1 Installing iDAQ modules into the iDAQ chassis ...

Page 19: ... operation If the input voltage is within OFF or ON state logic level a logic low 0 or high 1 will be sensed respectively If the input voltage is between the OFF and ON state logic levels the result is undetermined which may be low or high User should ensure the ON OFF state voltages of the sensors or switches meet the required values Do not input a voltage higher than the maximum value of ON stat...

Page 20: ...ng or not The universal digital output channel supports both sink NPN type and source PNP type connection as shown in Figure 2 3 Figure 2 3 Digital output signal connection For a sink type digital output the current which flows through the load is sunk by the digital output DO terminal and returns to the external source through the digital out put ground DOGND terminal This is shown in Figure 2 4 ...

Page 21: ...damaging The expected load current in amps can be calculated by the following equation where VEXT is the voltage of the external source in volts RLOAD is the load resistance in ohms and RINT is the internal resistance of the switch in ohms which can be found in the device specifications The device is also equipped with flyback diodes and resettable fuses polyswitches for each channel The flyback d...

Page 22: ...er higher than the minimum value of ON state or lower than the maximum value of OFF state for deterministic result If the input voltage is between these two values the result is undetermined which may be ON or OFF In addition do not input a voltage higher than the maximum allowable value of ON state or lower than the minimum allowable value of OFF state The device may be dam aged under such circum...

Page 23: ...configuration or digital output generation When performing digital output generation a voltage logic level is gener ated between the digital output DO terminal and the digital ground DGND termi nal This is shown in Figure 2 8 Figure 2 8 Digital output signal connection Each digital output channel can source or sink only finite amount of current If this limit is exceeded the output voltage will not...

Page 24: ...ource and the load current must be within the range as specified in A5 Solid State Relay SSR Output The device may be damaged if the voltage or current is beyond the maximum value The SSR provides galvanic isolation protection which can withstand a large continu ous voltage between external side and internal side This prevents device damage when such fault condition happens The device is also equi...

Page 25: ...assignment of iDAQ 731 iDAQ 751 Figure 2 11 Pin assignment of iDAQ 751 Pin Name Description Pin Number DICOM Digital input common point 1 2 19 20 DI n Digital input n n 0 15 3 18 DOCOM Digital output common point for source PNP type 21 22 DO n Digital output n n 0 15 23 38 DOGND Digital output ground for sink NPN type 39 40 ...

Page 26: ...output 10 38 DI O34 Digital input output 34 28 DI O11 Digital input output 11 58 DI O35 Digital input output 35 48 DI O12 Digital input output 12 15 DI O36 Digital input output 36 5 DI O13 Digital input output 13 36 DI O37 Digital input output 37 26 DI O14 Digital input output 14 56 DI O38 Digital input output 38 46 DI O15 Digital input output 15 14 DI O39 Digital input output 39 4 DI O16 Digital ...

Page 27: ...eld Application iDAQ 763D Figure 2 12 Pin assignment of iDAQ 763D Pin Name Description Pin Number RLY n A Solid state relay SSR n terminal A 3 5 7 17 23 25 27 37 RLY n B Solid state relay SSR n terminal B 4 6 8 18 24 26 28 38 NC Not connected 1 2 19 20 21 22 39 40 ...

Page 28: ...iDAQ 731_751_763D User Manual 18 ...

Page 29: ...Chapter 3 3 Function Details ...

Page 30: ...se refer to the soft ware manual 3 2 Trigger and Timing Signal Output According to the configuration the module can generate a start trigger signal and a stop trigger signal This will be described in the following sections 3 2 1 Digital Trigger One of the digital input channel can be selected as the signal source for the specified trigger signal The trigger signal can be configured as rising edge ...

Page 31: ...unction This section lists all the details about these functions 3 3 1 1 Digital Input Interrupt All digital input channels can generate software interrupts or events to notice the application about the state change of input signals Interrupts can occur at rising edge falling edge or both edges of the digital input signal as shown in Figure 3 3 Figure 3 4 and Figure 3 5 respectively The enable dis...

Page 32: ... pattern match interrupt will be generated as shown in Figure 3 6 Figure 3 6 Digital input pattern match interrupt for pattern 10xx0100 3 3 1 3 Digital Input Debounce Filter To prevent false interrupts due to noise or bouncing in the signal the digital input sig nals can be filtered If digital input filter is enabled transient signals with duration smaller than the filter duration will be consider...

Page 33: ...e device specifications for supported sample clock sources and the maximum allowable frequency of sample clock Figure 3 9 Digital input buffered hardware timed acquisition The acquired samples are first accumulated in the onboard first in first out FIFO memory of the device and then moved to the buffer in the PC by a direct memory access DMA engine A buffer is a block of memory in the PC for tempo...

Page 34: ...r acquisition 3 4 1 1 Post Trigger Acquisition A post trigger acquisition acquires a specified number of samples after the start trig ger The acquisition starts when a start trigger is received and automatically stops when the specified number of samples is acquired An example of 5 sample post trig ger acquisition is shown in Figure 3 10 Figure 3 10 Post trigger acquisition The start trigger can b...

Page 35: ...quisition The stop trigger can only be a hardware signal Refer to the device specifications for possible signal sources 3 4 1 3 About Trigger Acquisition An about trigger acquisition is the same as a pre trigger acquisition except that the time when the acquisition stops can be delayed by a specified number of sample clock cycles Figure 3 13 shows an example of a 5 sample about trigger acquisition...

Page 36: ...isition can also be delayed Refer to the device specifications for possible signal sources 3 4 3 Retriggerable Digital Input Acquisition The acquisition can be retriggerable When re trigger is enabled after the acquisition stops it restarts whenever the required trigger is received and reconfiguration of the acquisition is not required Figures 3 15 to 3 18 show examples of retrigger acquisition fo...

Page 37: ...AQ 731_751_763D User Manual Chapter 3 Function Details Figure 3 16 Pre trigger acquisition with retrigger Figure 3 17 About trigger acquisition with retrigger Figure 3 18 Streaming acquisition with retrigger ...

Page 38: ...tput Update With static digital output update the digital output state is updated only when the soft ware sends a write static digital output sample command The digital output state remains unchanged at other times This is shown in Figure 3 19 Figure 3 19 Static digital output update 3 5 2 Buffered Digital Output Waveform Generation With buffered digital output waveform generation the rate and dur...

Page 39: ... generation with delay Refer to section 3 1 Trigger and Timing Signal Output for possible signal routings and configurations for these timing signals start trigger stop trigger and sample clock Buffered digital output waveform generation has several advantages over static digi tal output update The start and stop time of generation or duration of the generation can be pre cisely controlled by hard...

Page 40: ...hen a start trigger is received and automatically stops when the specified number of samples is generated An example of 5 sample generation is shown in Figure 3 23 Figure 3 23 One buffered generation The start trigger can be a software command or a hardware signal If a hardware sig nal is used as the start trigger the start of generation can be delayed for a specified number of sample clock cycles...

Page 41: ...rigger or the stop for the stop trigger of the generation can also be delayed Refer to the device specifications for possible signal sources 3 6 3 Retriggerable Digital Output Generation The generation can be retriggerable When re trigger is enabled after the generation stops it restarts whenever the required trigger is received and reconfiguration of the generation is not required Figures 3 26 an...

Page 42: ...iDAQ 731_751_763D User Manual 32 Figure 3 27 Streaming generation with retrigger ...

Page 43: ...iate the modules in the iDAQ system It s given following a naming rule of combining chassis ID model name and slot number You can change the description in Navigator or just leave it as default The descrip tion is used in your own program in order to get control or device handler from the device Figure 3 28 Device description shown in Navigator ...

Page 44: ...iDAQ 731_751_763D User Manual 34 ...

Page 45: ...Appendix A A Specifications ...

Page 46: ...led or disabled by software independently Frequency 1 kHz max Other feature Latch digital input states when interrupt occurs Timing signal output to chassis From one of the digital input channels or dig ital input pattern match event software configurable A 2 TTL Digital Input iDAQ 751 Input logic level Logic high 2 3 V min Logic low 1 0 V max Working voltage 0 25 V 5 25 V Input protection voltage...

Page 47: ...e configurable Buffered output Update rate 10 kHz max software configurable Internal data buffer FIFO size 512 samples each sample contains state of all channels A 4 TTL Digital Output iDAQ 751 Output logic level Logic high 4 0 V min 2 mA source 5 2 V max Logic low 0 3 V max 2 mA sink Output current One channel 5 mA max All channels summed 64 mA max Isolation protection 60 VDC Response time 5 μs m...

Page 48: ...ware configurable Internal data buffer FIFO size 512 samples each sample contains state of all channels A 6 General Power consumption from chassis iDAQ 731 425 mW typ 450 mW max iDAQ 751 1050 mW typ 1500 mW max iDAQ 763D 225 mW typ 800 mW max Module dimensions 100 x 80 x 25 mm 3 94 x 3 15 x 0 98 in Operating temperature 20 C to 60 C 4 F to 140 F Storage temperature 40 C to 70 C 40 F to 158 F Opera...

Page 49: ...39 iDAQ 731_751_763D User Manual Appendix A Specifications A 7 Function Block iDAQ 731 iDAQ 751 iDAQ 763D ...

Page 50: ...iDAQ 731_751_763D User Manual 40 ...

Page 51: ...Appendix B B System Dimensions ...

Page 52: ...iDAQ 731_751_763D User Manual 42 B 1 iDAQ Modules ...

Page 53: ...43 iDAQ 731_751_763D User Manual Appendix B System Dimensions ...

Page 54: ...re subject to change without notice No part of this publication may be reproduced in any form or by any means such as electronically by photocopying recording or otherwise without prior written permission from the publisher All brand and product names are trademarks or registered trademarks of their respective companies Advantech Co Ltd 2021 ...

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