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FIGURE 1: DSPC-8682 SYSTEM BLOCK DIAGRAM .............................................................................. 9
FIGURE 2: DSPC-8682 PCI-E CARD PLACEMENT ............................................................................... 10
FIGURE 3: POWER DISTRIBUTION BLOCK DIAGRAM FOR DSP0, DSP1, DSP6 AND DSP7 .................... 11
FIGURE 4: POWER DISTRIBUTION BLOCK DIAGRAM FOR DSP2, DSP3, DSP4 AND DSP5 .................... 12
FIGURE 5: POWER DISTRIBUTION BLOCK DIAGRAM ....................................................................... 13
FIGURE 6: DSPC-8682 OVERALL POWER SEQUENCE ........................................................................ 15
FIGURE 7: POWER DISTRIBUTION ON DSPC-8682 PCI-E CARD ......................................................... 16
FIGURE8: DSPC-8682 CARRIER CLOCK FEEDING DIAGRAM .............................................................. 21
FIGURE9: DSPC-8682 RESET BLOCK DIAGRAM ................................................................................ 22
FIGURE10: THE DSP RESET SEQUENCE ON DSPC-8682 ..................................................................... 23
FIGURE11: TI TMS320C6678 BLOCK DIAGRAM................................................................................ 24
FIGURE12: SERIAL RAPIDIO RING ................................................................................................... 25
FIGURE13: PCIE INTERCONNECTION ............................................................................................... 26
FIGURE14: LAN INTERCONNECTION ............................................................................................... 27
FIGURE15: HYPERLINK CONNECTION ............................................................................................. 28
FIGURE16: FPGA CONNECTION ...................................................................................................... 29
FIGURE17: TOP SIDE LED LOCATION ............................................................................................... 30
FIGURE18: CONNECTOR OVERVIEW ............................................................................................... 32
FIGURE19:CN1, BOUNDARY SCAN FOR PEX748, BCM5482S AND CPS1616 ...................................... 33
FIGURE20: CN2, THE BOUNDARY SCAN FOR THE DSP FARM............................................................ 34
FIGURE21: CN3, TI 60-PIN EMULATION CONNECTOR....................................................................... 35
FIGURE22: CONNECTION THE XDS560V2 STM EMULATOR .............................................................. 35
FIGURE23: 60-PIN HEADER ORIENTATION ...................................................................................... 35
FIGURE24: THE CONNECTION WITH TI XDS560V2 STM EMULATOR ................................................. 36
FIGURE25: CN5, RJ45 LAN PORT ..................................................................................................... 37
FIGURE26: CN5, THE FPGA JTAG FOR FIRMWARE UPDATE .............................................................. 38
FIGURE27: CN6, 12V CONNECTOR .................................................................................................. 39
FIGURE28: CN7, FAN CONNECTOR .................................................................................................. 40
FIGURE29: CN8, FAN CONNECTOR .................................................................................................. 41
FIGURE30: THE SW1 ON DSPC-8682 PCIE CARD .............................................................................. 42
