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2.4
Power Sequence
DSPC-8682 consists of many devices on it, including DSP, PCIe switch, SRIO switch, PHY & FPGA etc.
Hence, the power sequence is designed to meet all devices’ power-on requirements. And the timing
parameters are shown in below table (Table 2.System Power Sequence Parameter) while the power
sequence is shown in below figure.( Figure 6.DSPC-8682 overall power sequence).
Figure 6: DSPC-8682 overall power sequence
t<1ms
Hos t re se t from PC
DVDD1P2_EN
5ms < t <200ms
VCC1P2
IDT1616
5ms < t <200ms
IDT1616
VCC0P9
EN_VCC0P9
CPS1432_SRIO_RST#
PEX8748
BCM5482S
PEX8748
t<1ms
PEX8748_PCIE_RST#
POWER_GOOD
Delay 100ms
3.3V standby
pow er
3VSB
FPGA
VCC1P5
EN_VCC1P5
VCC0P75
VCC2P5
EN_VCC2P5
5ms < t <200ms
5ms < t <200ms
5ms < t <200ms
CVDD_DSP
UCD9244_EN
VCC1P0_1
EN_VCC1P0_1
DVDD1P8
EN_DVDD1P8
1V2SB
1.2VSB
TMS320C6678
TMS320C6678
TMS320C6678
VCC3
EN_VCC3
BCM5482S
BCM5482S
IDT1616
T>1m s
POR#
CLOCK_PLL_LOCK
RESETSTAT#
T>1m s
REFCLKP&N
DDRCLKP&N
RESET#
RESETFULL#
T>1ms
PCIE_GF_RST#
5482S_PHY_RST#
t<1ms
VCC3_1616
EN_VCC3_1616
EN_VCC1P0_2
VCC1P0_2
VCC3_PCIE_CLK
EN_VCC3_PCIE_CLK
VCC1V8_FPGA
FPGA
FPGA
TMS320C6678
VCC12
5VSB
