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2.7
Reset Sequence
Below figure is provided by TMS320C6678 data manual which describes the reset timings related to
DSP power rails (CVDD, CVDD1, DVDD15 and DVDD18), reference clocks (core clock and DDR3 clock)
and three reset events (RESETz, PORz and RESETFULLz). User can refer to TMS320C6678 Data Manual
on TI webpage for the details.
Figure10: The DSP Reset Sequence on DSPC-8682
