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Figure16: FPGA connection
CLK
MISO
CS0#
PXE8748_INT
CS2#
CS1#
MOSI
INT
PXE8748_SCLK
PXE8748_CS2
PXE8748_CS1
PXE8748_CS0
+V1.8
BROADCOM
BCM5482SHA1KFBG
PXE8748_MISO
PXE8748_MOSI
PHY1_LED3
+V3.3
PHY1_LED2
PHY1_LED4
PHY1_LED1
PHY2_LED3
PHY2_LED4
PHY2_LED2
PHY2_LED1
PXE8748_PCIE_RST#
5482S_PHY_RST#
CPS1616_RST#
5482S_LAN1_ACT
PXE8748
5482S_LAN1_LINK
5482S_LAN1_SPEED1
5482S_LAN1_SPEED2
BCM5482S
CPS1616
5482S_LAN2_LINK
5482S_LAN2_SPEED1
5482S_LAN2_SPEED2
5482S_LAN2_ACT
BROADCOM
IDT
PLX
UCD9244 x 2
PG_VCC0P9
VCC5
RT2
RT1
FAN_PWM
PG_VCC5
EN_VCC1P0_2
PG_VCC1P0_2
EN_VCC5
SPI
FPGA
TI_CDCLVD110ARHBR
W83795ADG
SDA_HM
CLK_48M_HM
SCL_HM
HM_ALERT#
CLK_Buf_EN1[0:3]
CLK_Buf_SI1[0:3]
CLK_Buf_CK[0:3]
DVDD_1P8
VCC0P9
VCC1P2
VCC1P5
VCC1P0
VCC3
VCC2P5
Temp_DSP4_7
Hardware
Montor
Temp_DSP0_3
EN_VCC1P0_1
EN_VCC3
EN_VCC2P5
EN_DVDD1P8
EN_VCC0P9
EN_VCC1P2
PG_CVDD0_3
EN_VCC1P5
POR#
RESET#
RESETFULL#
HOUT
BOOTCOMPLETE
Control
Sequences
Power
Configurations
CLOCK
FPGA_JTAG_TMS
FPGA_JTAG_TDO
FPGA_JTAG_TDI
configurations
Boot & Device
FPGA
JTAG
Control
RESET &
DSP
DSP
Interrupts
Control
PHY
DSP_RESET#
DSP_RESETFULL#
DSP_POR#
DSP_HOUT
DSP_BOOTCOMPLETE
+V3.3
+V1.8
RJ45[1:2]
XILINX_XC3S200AN
RESET
+V3.3
+V3.3
+V1.8
PCIE_GF_RST#
FPGA_JTAG_TCK
DSP_GPIO[0 : 15]
GPIO[0:15]
DSP
TMS320C6678
PLX
PEX8748
MPS_MP28253EL x4
VOLTERRA_VT237 x4
Power Group
PG_DVDD1P8
PG_VCC1P5
PG_CVDD4_7
PG_VCC1P0_1
+V3.3
PG_VCC3
PG_VCC1P2
PG_VCC2P5
62005_CLOCK_PLL_LOCK
62005_CLK_SSP_MISO
TI_CDCE62005
+V3.3
62005_CLK_SSP_CS0
62005_CLK_SSP_CLK
CLOCK Group
62005_CLK_SSP_Power_down#
62005_CLK_SSP_MOSI