51
Chapter 3
Inter(R) speedstep(tm) tech
Intel SpeedStep Technology centralizes the control mechanism in the
processor, eliminating the need for coordination with the chipset during
the frequency/voltage configuration. This option is used to enable/disable
the GV3 bit.
3.3.2 IDE Configuration
Figure 3.6: IDE Configuration
ATA/IDE Configuration
This can be configured as Disabled, Compatible or Enhanced.
Configure SATA as
This can be configured as IDE, RAID or AHCI. RAID will be activated
by the ICH8M-E only.
Primary IDE Master
While entering setup, the BIOS automatically detects the presence of IDE
devices. This displays the status of IDE device auto-detection.
Summary of Contents for AIMB-556
Page 14: ...AIMB 556 User Manual xiv...
Page 15: ...1 Chapter1 CHAPTER 1 Hardware Configura tion...
Page 31: ...17 Chapter2 CHAPTER 2 Connecting Peripherals...
Page 58: ...AIMB 556 User Manual 44...
Page 59: ...45 Chapter3 CHAPTER 3 AMI BIOS Setup...
Page 74: ...AIMB 556 User Manual 60 3 5 Boot Setup Utility Figure 3 13 Boot Setup Utility...
Page 77: ...63 Chapter3 3 7 Advanced Chipset Settings Figure 3 16 Advanced Chipset Settings...
Page 83: ...69 Chapter4 CHAPTER 4 Chipset Software Installation Utility...
Page 89: ...75 Chapter5 CHAPTER 5 VGA Setup...
Page 94: ......
Page 95: ...81 Chapter6 CHAPTER 6 Onboard Security Setup...
Page 99: ...85 Chapter6 4 Click Next when you see the following message...
Page 102: ...AIMB 556 User Manual 88...
Page 103: ...89 Chapter7 CHAPTER 7 LAN Configuration...
Page 108: ...AIMB 556 User Manual 94...
Page 109: ...95 AppendixA Appendix A Programming the Watchdog Timer...
Page 119: ...Appendix B I O Pin Assignments...
Page 142: ...AIMB 556 User Manual 128...