ADLINK Technology SMARC NXP i.MX8M-plus Quad NPU User Manual Download Page 4

Page: 4 / 62

LEC-

iMX8M plus User’s Guide 1.0

SGET SMARC Rev 2.1

Page 4

Revision

Description

Date (dd/mm/yyyy)

Author

0.8

Preliminary engineering version updated

05/04/2020

0.9

Preliminary engineering version updated

22/01/2021

1.0

Release version

01/02/2020

1.0.1

Change HDMI_HPD to runtime and PD 1M

24/9/2021

Summary of Contents for SMARC NXP i.MX8M-plus Quad NPU

Page 1: ...LEC IMX8MP 02 01 2021...

Page 2: ...ct descriptions at any time without notice Environmental Responsibility ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the Europea...

Page 3: ...ty Keep equipment properly ventilated do not block or cover ventilation openings Make sure to use recommended voltage and power source settings Always install and operate equipment near an easily acce...

Page 4: ...ADLINK Technology Inc Revision Description Date dd mm yyyy Author 0 8 Preliminary engineering version updated 05 04 2020 HP 0 9 Preliminary engineering version updated 22 01 2021 HP 1 0 Release versi...

Page 5: ...er 13 2 9 Debug Header 13 2 10 Boot Modes 13 2 11 Power 14 2 12 Mechanical and Environmental 14 3 Block Diagram 15 4 Pinout and Signal Descriptions 16 4 1 Pin Summary 16 4 2 Signal Terminology Descrip...

Page 6: ...41 4 4 3 CAN bus 42 4 4 4 Miscellaneous 42 4 4 5 Power and System Management 43 4 4 6 DB30 Multipurpose Connector 44 4 4 7 Boot Select 45 4 4 8 Power 46 4 5 SMARC pin to controller mapping 47 5 Softwa...

Page 7: ...LEC iMX8M plus User s Guide 1 0 SGET SMARC Rev 2 1 Page 7 copyright 2021 ADLINK Technology Inc List of Figures Figure 1 Module function diagram 15 Figure 2 Module top botom side pin numbering 17...

Page 8: ...mm The Module PCBs have 314 edge fingers that mate with a low profile 314 pin 0 5 mm pitch right angle connector the connector is sometimes identified as a 321 pin connector but 7 pins are lost to th...

Page 9: ...Device Microchip ATECC608A optional Cryptographic co processor with secure hardware based key storage Protected storage for up to 16 Keys certificates or data ECDH FIPS SP800 56A Elliptic Curve Diffi...

Page 10: ...ons VPU 1080p60 HEVC H 265 H 264 VP9 Decoder 1080p60 AVC H 264 HEVC H 265 encoder NPU selected parts 2 3 TOP s Neural Network performance Keyword detect noise reduction beamforming Speech recognition...

Page 11: ...VB and IEEE 1588 Supports 10 100 1000 Mbps data transfer rates both full duplex and half duplex 2 5 1216 M 2 LGA WIFI optional LEC IMX8MP can be equipped with an optional WIFI LGA module In case of no...

Page 12: ...and SER1 SER3 optional Tx Rx 7 or 8 bit data words 1 or 2 stop bits programmable parity even odd or none Programmable baud rates up to 4 Mbps CAN bus Supporting dual CAN2 0B only or mixed CAN2 0B and...

Page 13: ...mp range Compatible with eMMC specification 4 41 4 51 and 5 0 2 8 SEMA Board Management Controller Voltage current monitoring boot configuration logistics and forensic information flat panel control w...

Page 14: ...T SMARC Specifications v2 1 Dimension SMARC small size module 82mm x 50mm Operating Temperature Standard 0 C to 60 C Rugged 40 C to 85 C optional Humidity 5 90 RH operating non condensing 5 95 RH stor...

Page 15: ...CAM1 GPIO NXP iMX 8M plus USB1 2 0 OTG USB2 3 0 Host MIPI CSI 2 lanes MIPI CSI 4 lanes LVDS0 DSI0 LVDS1 HDMI 2 0a USB HUB 2x USB 3 0 2 0 3x USB 2 0 MIPI MUX PCIe Switch ECSPI1 ECSPI2 SDHC2 1x PCIe x1...

Page 16: ...t and Signal Descriptions 4 1 Pin Summary The below table is a comprehensible list of all signal pins on the MXM 3 connector in the standard specification SMARC 2 1 Those signals not supported on LEC...

Page 17: ...GND P25 GBE0_LINK_ACT S26 GBE1_MDI3 P26 GBE0_MDI1 S27 GBE1_MDI3 P27 GBE0_MDI1 S28 GBE1_CTREF P28 GBE0_CTREF S29 PCIE_D_TX SERDES_1_TX P Pin Primary Top Side S Pin Secondary Bottom Side P29 GBE0_MDI0...

Page 18: ...PCIE_A_TX S91 PCIE_B_TX P91 GND S92 GND P92 HDMI_D2 DP1_LANE0 S93 DP0_LANE0 P93 HDMI_D2 DP1_LANE0 S94 DP0_LANE0 P94 GND S95 DP0_AUX_SEL P95 HDMI_D1 DP1_LANE1 S96 DP0_LANE1 P96 HDMI_D1 DP1_LANE1 S97 DP...

Page 19: ...SI0_CLK P135 SER1_RX S136 GND P136 SER2_TX S137 LVDS0_3 eDP0_TX3 DSI0_D3 P137 SER2_RX S138 LVDS0_3 eDP0_TX3 DSI0_D3 P138 SER2_RTS S139 I2C_LCD_CK P139 SER2_CTS S140 I2C_LCD_DAT P140 SER3_TX S141 LCD0_...

Page 20: ...Signal for MIPI CSI 2 cameras and DSI displays LVDS M PHY Low Voltage Differential Signal for MIPI CSI 3 cameras LVDS LCD Low Voltage Differential Signal for LCD displays LVDS PCIE Low Voltage Differe...

Page 21: ...DSI0_D2 DSI0_D2 DSI0_D3 DSI0_D3 eDP0_TX0 eDP0_TX0 eDP0_TX1 eDP0_TX1 eDP0_TX2 eDP0_TX2 eDP0_TX3 eDP0_TX3 S111 S112 S114 S115 S117 S118 S120 S121 LVDS1_0 LVDS1_0 LVDS1_1 LVDS1_1 LVDS1_2 LVDS1_2 LVDS1_3...

Page 22: ...channel power enable active high O CMOS 1 8V Runtime LCD0_BKLT_EN S127 Primary LVDS channel backlight enable active high O CMOS 1 8V Runtime LCD0_BKLT_PWM S141 Primary LVDS channel brightness control...

Page 23: ...ame Pin Description I O Type I O Level Power Domain PU PD Comments DSI0_D0 DSI0_D0 DSI0_D1 DSI0_D1 DSI0_D2 DSI0_D2 DSI0_D3 DSI0_D3 S125 S126 S128 S129 S131 S132 S137 S138 Primary DSI panel differentia...

Page 24: ...ames DP signal names P92 P93 P95 P96 P98 P99 HDMI_D2 HDMI_D2 HDMI_D1 HDMI_D1 HDMI_D0 HDMI_D0 DP1_LANE0 DP1_LANE0 DP1_LANE1 DP1_LANE1 DP1_LANE2 DP1_LANE2 P101 P102 HDMI_CK HDMI_CK DP1_LANE3 DP1_LANE3 S...

Page 25: ...pair clock lines O TMDS HDMI Runtime HDMI_CTRL_CK P105 I2C_CLK line dedicated to HDMI O OD COMS 1 8V Runtime PU 2 2 Level shifter FET and 5V PU resistor shall be placed between the module and the HDMI...

Page 26: ..._DAT CSI0_TX S7 I2C data for serial camera data support link or differential data lane I O OD CMOS O LVDS M PHY 1 8V Runtime PU 2 2K MIPI CSI 2 0 uses I2C_CAM0_DAT MIPI CSI 3 0 uses CSI0_TX I2C_CAM0_C...

Page 27: ...support link or differential data lane I O OD CMOS O LVDS M PHY 1 8V Runtime PU 2 2K MIPI CSI 2 0 mode uses I2C_CAM1_DAT MIPI CSI 3 0 mode uses CSI1_TX I2C_CAM1_CK CSI1_TX S1 I2C clock for serial came...

Page 28: ...O CMOS 1 8V Runtime Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode I2S2_LRCK S50 I2S2 Left Right synchronization clock I O CMOS 1 8V Runtime Module Output if CPU acts...

Page 29: ...or port 1 I O USB USB Runtime From USB HUB USB1_EN_OC P67 USB over current sense for port 1 I O OD CMOS 3 3Vsb 3 3V Runtime PU 10k Pulled low by Module OD driver to disable USB0 power Pulled low by Ca...

Page 30: ...4 Input pin to announce OTG device insertion on USB 3 0 port I CMOS 3 3Vsb 3 3V Runtime USB4 USB4 S35 S36 USB differential data pairs for port 4 I O USB USB Runtime USB4_EN_OC P76 USB over current sen...

Page 31: ...signal because module provides onboard PCIe clock PCIE_B_TX PCIE_B_TX S90 S91 Differential PCIe link B transmit data pair O LVDS PCIE Runtime Series AC coupled on module PCIE_B_RX PCIE_B_RX S87 S88 Di...

Page 32: ...S29 S30 Differential PCIe link D transmit data pair O LVDS PCIE Runtime Series AC coupled on module PCIE_D_RX PCIE_D_RX S32 S33 Differential PCIe link D receive data pair I LVDS PCIE Runtime Series A...

Page 34: ...B RX RX MDI 2 B1_DC MDI 3 B1_DD GBE MDI Runtime Twisted pair signals for external transformer GBE0_LINK100 P21 Link Speed Indication LED for GBE 0 100Mbps O OD CMOS 3 3V Runtime Shall be able to sink...

Page 35: ...MDI 2 B1_DC MDI 3 B1_DD GBE MDI Runtime Twisted pair signals for external transformer GBE1_LINK100 S19 Link Speed Indication LED for GBE 1 100Mbps O OD CMOS 3 3V Runtime Shall be able to sink 24mA or...

Page 36: ...mand Response This signal is used for card initialization and for command transfers During initialization mode this signal is open drain During command transfer this signal is in push pull mode I O CM...

Page 37: ...I CMOS 1 8V Standby also referred to as MISO SPI0_DO P46 SPI0 Master output Slave input O CMOS 1 8V Standby also referred to as MOSI SPI1_CS0 P54 SPI1 Master Chip Select 0 O CMOS 1 8V Standby See ESP...

Page 38: ...aster to eSPI slaves ESPI_ALERT0 ESPI_ALERT1 S43 S44 ESPI ALERT I OD CMOS 1 8V Standby This pin is used by eSPI slave to request service from eSPI master Alert is an open drain output from the slave T...

Page 39: ...in a single big list Below is an overview of all I2C busses and where to find them Name Pin Description Where to find I2C_LCD_DAT S140 DDC data line used for flat panel detection and control LVDS DSI...

Page 40: ...8V Runtime PU 470K on the Module Default use is GPIO3 alternative use is Camera 1 Reset active low through DTS GPIO4 HDA_RST P112 General purpose I O pin 4 I O CMOS 1 8V Runtime PU 470K on the Module...

Page 41: ...andshake line for port 0 I CMOS 1 8V Runtime SER1_TX P134 Asynchronous serial data output port 1 O CMOS 1 8V Runtime SER1_RX P135 Asynchronous serial data input port 1 I CMOS 1 8V Runtime SER2_TX P136...

Page 42: ...1 8V Runtime CAN1_RX P146 CAN port1 Receive input I CMOS 1 8V Runtime 4 4 4 Miscellaneous Name Pin Description I O Type I O Level Power Domain PU PD Comments TEST S157 Held low by Carrier to invoke M...

Page 43: ...me PU 4 7K Driven by OD on Carrier Pulled up on module VIN_PWR_BAD S150 Power bad indication from Carrier board Module and Carrier power supplies other than Module and Carrier power supervisory circui...

Page 44: ...rier Pulled up on module I2C_PM_DAT P122 Power management I2C bus DATA I O OD CMOS 1 8V Runtime PU 2k2 On x86 systems these serve as SMB DATA Pulled up on module I2C_PM_CK P121 Power management I2C bu...

Page 45: ...CMOS 1 8Vsb Standby PU 10K Driven by OD on Carrier Pulled up on module Low on this pin allows non protected segments of Module boot device to be rewritten restored from an external USB Host on Module...

Page 46: ...5V GND P2 P9 P12 P15 P18 P32 P38 P47 P50 P53 P59 P68 P79 P82 P85 P88 P91 P94 P97 P100 P103 P120 P133 P142 S3 S10 S16 S25 S34 S47 S61 S64 S67 S70 S73 S80 S83 S86 S89 S92 S101 S110 S119 S124 S130 S136 S...

Page 48: ...X1 In LVDS D PHY i MX8Mplus MIPI_CSI2_D1_N CSI_P2_VDDHA P12 GND P13 CSI1_RX2 In LVDS D PHY i MX8Mplus MIPI_CSI2_D2_P CSI_P2_VDDHA P14 CSI1_RX2 In LVDS D PHY i MX8Mplus MIPI_CSI2_D2_N CSI_P2_VDDHA P15...

Page 49: ...ir SD2 3 3V i MX8Mplus SD2_DATA3 ALT0 NVCC_SD2 P43 SPI0_CS0 Out SPI 1 8V i MX8Mplus ECSPI2_SS0 ALT0 NVCC_ECSPI P44 SPI0_CK Out SPI 1 8V i MX8Mplus ECSPI2_SCLK ALT0 NVCC_ECSPI P45 SPI0_DIN In SPI 1 8V...

Page 50: ...N C P73 RSVD N C N C P74 USB3_EN_OC In GPIO 3 3V USB Hub FL5500 2F0 DS1_OVRCURR AVDD33 P75 PCIE_A_RST Out GPIO 3 3V i MX8Mplus SAI1_TXC ALT5 NVCC_SAI1 P76 USB4_EN_OC In GPIO 3 3V USB Hub FL5500 2F0 D...

Page 51: ...IO P106 HDMI_CTRL_DAT DP1_AUX Bi Dir PU 2 2K PD 100K HDMI i MX8Mplus HDMI_DDC_SDA H HDMI_AUXN L HDMI_AVDDIO P107 DP1_AUX_SEL Out PD 1M HDMI TS5A23159RSER P108 GPIO0 CAM0_PWR Out PU 470K GPIO 1 8V i MX...

Page 52: ...UART 1 8V i MX8Mplus NAND_CE0_B ALT1 NVCC_NAND P135 SER1_RX In UART 1 8V i MX8Mplus NAND_ALE ALT1 NVCC_NAND P136 SER2_TX Out UART 1 8V i MX8Mplus UART4_TXD ALT5 NVCC_UART P137 SER2_RX In UART 1 8V i M...

Page 53: ...Mplus MIPI_CSI1_CLK_P MIPI_CSI1_VDDHA S9 CSI0_CK In MIPI CSI i MX8Mplus MIPI_CSI1_CLK_N MIPI_CSI1_VDDHA S10 GND S11 CSI0_RX0 In MIPI CSI i MX8Mplus MIPI_CSI1_D0_P MIPI_CSI1_VDDHA S12 CSI0_RX0 In MIPI...

Page 54: ...0 NVCC_SAI2 S40 I2S0_SDOUT Out SAI 1 8V i MX8Mplus SAI2_TXD0 ALT0 NVCC_SAI2 S41 I2S0_SDIN In SAI 1 8V i MX8Mplus SAI2_RXD0 ALT0 NVCC_SAI2 S42 I2S0_CK Bi Dir SAI 1 8V i MX8Mplus SAI2_TXC ALT0 NVCC_SAI2...

Page 55: ...TX Out Serial 0 1uF USB USB Hub FL5500 2F0 DS0_TXP S72 USB2_SSTX Out Serial 0 1uF USB USB Hub FL5500 2F0 DS0_TXM S73 GND S74 USB2_SSRX In USB USB Hub FL5500 2F0 DS0_RXP S75 USB2_SSRX In USB USB Hub FL...

Page 56: ...S101 GND S102 DP0_LANE3 N C N C S103 DP0_LANE3 N C N C S104 USB3_OTG_ID N C N C S105 DP0_AUX N C N C S106 DP0_AUX N C N C S107 LCD1_BKLT_EN Out GPIO 1 8V i MX8Mplus GPIO1_IO00 S108 LVDS1_CK eDP1_AUX...

Page 57: ...GND S125 LVDS0_0 eDP0_TX0 DSI0_D0 Out Serial 0R LVDS i MX8Mplus A_Y0P S126 LVDS0_0 eDP0_TX0 DSI0_D0 Out Serial 0R LVDS i MX8Mplus A_Y0N S127 LCD0_BKLT_EN Out GPIO 1 8V i MX8Mplus GPIO1_IO10 S128 LVDS...

Page 58: ...MC PC14 S143 GND S144 eDP0_HPD DSI0_TE In PD 1M GPIO 1 8V i MX8Mplus SAI3_RXC ALT0 NVCC_SAI3 S145 WDT_TIME_OUT Out GPIO 1 8V BMC PD2 1V8SMC S146 PCIE_WAKE In GPIO 3 3V i MX8Mplus SAI1_TXFS ALT5 NVCC_S...

Page 59: ...5 Software Support 5 1 1 Uboot Yocto Goto https github com adlink Yocto source code and compiling instructions are available 5 1 2 Ubuntu Build instruction from source are available on Github 5 1 3 An...

Page 62: ...yright 2021 ADLINK Technology Inc 7 Thermal Solutions For optimum performance LEC IMX8M has to be cooled by a passive Heatsink Heat spreader optionally available for ordering HTS sIMX8MP Heatspreader...

Search results

Summary of Contents for SMARC NXP i.MX8M-plus Quad NPU

Reviews:

Related manuals for SMARC NXP i.MX8M-plus Quad NPU

Brands by name

Popular brands

ADLINK Technology SMARC NXP i.MX8M-plus Quad NPU, User Manual

Search results

Summary of Contents for SMARC NXP i.MX8M-plus Quad NPU

Reviews:

Related manuals for SMARC NXP i.MX8M-plus Quad NPU

Brands by name

Popular brands