ADLINK Technology SMARC NXP i.MX8M-plus Quad NPU, User Manual

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LEC- iMX8M plus User’s Guide 1.0 SGET SMARC Rev 2.1
Page 27
copyright © 2021 ADLINK Technology Inc.
4.3.3.2 MIPI CSI1 (Camera)
Name Pin # Description I/O
Type I/O
Level Power
Domain PU / PD Comments
C
CSI1_RX0-
C
CSI1_RX1-
C
CSI1_RX2-
C
CSI1_RX3- P7
P8
P10
P11
P13
P14
P16
P17 CSI1 differential input (point to point) I LVDS D-PHY
/ I LVDS M-PHY Runtime
CSI1_CK- P3
P4 CSI1 differential clock input (point to
point) I LVDS D-PHY Runtime
I2C_CAM1_DAT /
CSI1_TX- S2 I2C data for serial camera data
support link or differential data lane I/O OD CMOS
/ O LVDS M-
PHY 1.8V Runtime PU 2.2K MIPI-CSI 2.0 mode uses I2C_CAM1_DAT
MIPI-CSI 3.0 mode uses CSI1_TX-
I2C_CAM1_CK /
S1 I2C clock for serial camera data
support link or differential data lane O OD CMOS
/ O LVDS M-
PHY 1.8V Runtime PU 2.2K MIPI-CSI 2.0 mode uses I2C_CAM1_CK
MIPI-CSI 3.0 mode uses
CAM1_PWR# /
GPIO1 P109 Camera 0 Power Enable, active low
output. O CMOS 1.8V Runtime CAM1_PWR# is default, GPIO1 can be enabled
through DVT
CAM1_RST# /
GPIO3 P111 Camera 0 reset, active low output O CMOS 1.8V Runtime CAM1_PWR# is default, GPIO3 can be enabled
through DVT
CAM_MCK S6 Master clock output O CMOS 1.8V Runtime This signal is used by both CSI0 and CSI1