LEC-
PX30 User’s Guide
SGET SMARC Rev 2.1
Page 21
copyright © 2020 ADLINK Technology Inc.
4.3.1.1
LVDS0 mode
Name
Pin # Description
I/O
Type
I/O
Level
Power
Domain
PU /
PD
Comments
LVDS0_0-
LVDS0_1 -
LVDS0_2-
LVDS0_3-
S125
S126
S128
S129
S131
S132
S137
S138
Primary LVDS channel differential pair
data lines
O LVDS
LCD
Runtime
L
LVDS0_CK-
S134
S135
Primary LVDS channel differential pair
clock lines
O LVDS
LCD
Runtime
LCD0_VDD_EN
S133 Primary LVDS channel power enable,
active high
O
CMOS
1.8V
Runtime
LCD0_BKLT_EN
S127 Primary LVDS channel backlight enable,
active high
O
CMOS
1.8V
Runtime
LCD0_BKLT_PWM
S141 Primary LVDS channel brightness control
through pulse width modulation (PWM)
O
CMOS
1.8V
Runtime
I2C_LCD_DAT
S140 DDC data line used for flat panel
detection and control
I/O OD
CMOS
1.8V
Runtime PU 2k2
I2C_LCD_CK
S139 DDC clock line used for flat panel
detection and control
O OD
CMOS
1.8V
Runtime PU 2k2
