nanoX-EL User’s Guide
PICMG COM.0 R3.0
Page 29
Copyright © 2021 ADLINK Technology, Inc.
4.3.3.1.
DisplayPort (DP) Mode
Name
Pin #
Description
I/O
PU / PD
Comment
DP
DP0_LANE0-
DP
DP0_LANE1-
DP
DP0_LANE2-
DP
DP0_LANE3-
B71
B72
B73
B74
B75
B76
B81
B82
DP Port 1, differential pair data lines
O PCIE
AC coupled off Module
100 nF DC blocking capacitors shall be placed on
the Carrier
DP0_HPD
B89
DP Port 1, detection of Hot Plug / Unplug and
notification of the link layer
I 3.3V
PD 100K
Module must tolerate high level in stand-by mode.
The carrier board shall include a blocking FET on
DP1_HPD to prevent back-drive current from
damaging the Module.
B98
DP Port 1, Bidirectional Channel used for Link
Management and Device Control
I/O PCIE
PD 100K
AC coupled on Module
DP0_AUX-
B99
DP Port 1, Bidirectional Channel used for Link
Management and Device Control
I/O PCIE
PU 100K
AC coupled on Module
DDI0_DDC_AUX_SEL
B95
Strapping Signal to select HDMI or DP output
1M pull-down to logic ground enables HDMI
Floating enables DisplayPort mode
I 3.3V
DP mode enabled
