ADLINK Technology nanoX-EL User Manual Download

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nanoX-EL User’s Guide

PICMG COM.0 R3.0

Page 1

nanoX-EL

Revision:

Rev. 0.1 Preliminary

Date:

2021-11-11

Part Number:

50M-00055-1000

User’s Guide

Summary of Contents for nanoX-EL

Page 2: ...trical and Electronic Equipment WEEE directive Environmental protection is a top priority for ADLINK We have enforced measures to ensure that our products manufacturing processes components and raw ma...

Page 3: ...cables when installing mounting or un installing removing equipment To avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from high...

Page 4: ...oting special levels of information Note This information adds clarity or specifics to text and illustrations Caution This information indicates the possibility of minor physical injury component dama...

Page 6: ...6 Multi I O and Storage 13 2 7 Trusted Platform Module TPM 15 2 8 SEMA Board Controller 15 2 9 Debug 15 2 10 Power 15 2 11 Mechanical and Environmental 16 3 Block Diagram 17 4 Pinout and Signal Descri...

Page 7: ...ional Features 45 5 1 Debug Connector 46 5 2 Status LEDs 47 5 3 Exception Codes 48 5 4 BIOS Boot Select 49 6 BIOS Checkpoints Beep Codes 50 7 Software Support 51 7 1 1 Windows 10 IOT Enterprise 64 bit...

Page 8: ...igure 2 Module rear side row and pin numbering 18 Figure 3 Module feature locations 45 Figure 4 nanoX EL and Debug Module 46 Figure 5 Module mechanical dimensions 52 Figure 6 Heatspreader Bottom Mount...

Page 9: ...p that provides ECC level error correction A maximum 16GB LPDDR4 memory capacity wide operating temperature range and MIL STD environmental specifications make it well suited for mission critical or e...

Page 10: ...ECC non ECC Intel TCC Intel Atom x6200FE 1 0 GHz 4 5W 2C No GPU IBECC non ECC Intel TCC Intel Pentium J6426 2 0 3 0 GHz 10W 4C 32EU non ECC Intel Celeron J6413 1 8 3 0 GHz 10W 4C 16EU non ECC Intel Pe...

Page 11: ...CMOS backup in 16MB or 32MB TBC MB SPI BIOS dual BIOS by build option 2 2 Video GPU Intel Gen 11 LP Graphics core architecture GPU Feature Support 2 independent and simultaneous combinations of Displ...

Page 12: ...dual channel 18 24 bit LVDS through eDP to LVDS IC supports DE mode and Hsync Vsync mode Max resolution 1920x1200 60Hz in dual mode Pixel clock frequency up to 112 MHz VESA and JEIDA panel data format...

Page 13: ...eed USB signalling Note Carrier board must be designed for Gen2 operation UART Two UART interfaces SER0 and SER1 RX TX on module Console Redirection COM 1 or COM 2 selectable in BIOS Up to 4 serial po...

Page 14: ...3V SD cards only SATA 2x SATA 6Gb s SATA 0 1 eMMC 16 32 64GB Note Boot device support may vary between operating systems Combinations CPU SKUs memory capacity eMMC capacity not listed as standard wil...

Page 15: ...port watchdog timer and fan control 2 9 Debug 30 pin flat cable connector for use with DB 30 x86 debug module Supports BIOS POST code LED embedded controller access SPI BIOS flashing internal power ra...

Page 16: ...ini size 84 x 55 mm Operating Temperature Standard 0 C to 60 C Wide Voltage Input Storage 20 C to 80 C Extreme Rugged 40 C to 85 C Standard Voltage Input Storage 40 C to 85 C Selected SoC SKUs Humidit...

Page 17: ...5 211 DDI 0 eDP LVDS USB 3 0 Lane 0 1 USB 2 0 Lane 0 7 SATA Port 0 1 Max 2 5GbE PCIe Lane 0 3 HDA SPI SMBus I2C GPIO SDIO UART 0 1 CAN LPC eSPI 2 USB 3 0 4 PCIe Gen3 x4 x2 x1 config eSPI build option...

Page 18: ...ble below is a comprehensive list of all signal pins supported on the single 220 pin COM Express connectors as defined for Type 10 in the PICMG COM 0 R3 0 specification Signals described in the specif...

Page 19: ...FIXED A12 GBE0_MDI0 B12 PWRBTN A13 GBE0_MDI0 B13 SMB_CK A14 GBE0_CTREF B14 SMB_DAT A15 SUS_S3 B15 SMB_ALERT A16 SATA0_TX B16 SATA1_TX A17 SATA0_TX B17 SATA1_TX A18 SUS_S4 B18 SUS_STAT ESPI_RESET A19...

Page 20: ...EN A48 RSVD B48 USB0_HOST_PRSNT A49 GBE0_SDP B49 SYS_RESET A50 LPC_SERIRQ ESPI_CS1 B50 CB_RESET A51 GND FIXED B51 GND FIXED A52 RSVD B52 RSVD A53 RSVD B53 RSVD A54 GPI0 B54 GPO1 A55 RSVD B55 RSVD A56...

Page 21: ...AIR3 A83 LVDS_I2C_CK eDP_AUX B83 LVDS_BKLT_CTRL eDP_BKLT_CTRL A84 LVDS_I2C_DAT eDP_AUX B84 VCC_5V_SBY A85 GPI3 B85 VCC_5V_SBY A86 RSVD B86 VCC_5V_SBY A87 eDP_HPD B87 VCC_5V_SBY A88 PCIE0_CK_REF B88 BI...

Page 22: ..._12V A107 VCC_12V B107 VCC_12V A108 VCC_12V B108 VCC_12V A109 VCC_12V B109 VCC_12V A110 GND FIXED B110 GND FIXED Note STRIKETHROUGH strike through entries are not supported functions on this product e...

Page 23: ...V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3VSB Input or output 3 3V tolerant active in standby state DDC Display Data Channel PCIE PCI Express compatible differential signal PEG PCI Ex...

Page 24: ...t to CODEC active low O 3 3VSB AC_SYNC HDA_SYNC A29 Sample synchronization signal to the CODEC s O 3 3V AC_BITCLK HDA_BITCLK A32 Serial data clock generated by the external CODEC s I O 3 3V AC_SDOUT H...

Page 25: ...ignals directly eDP vs LVDS pin mapping is described below Pin LVDS mode eDP mode A71 A72 LVDS_A0 LVDS_A0 eDP_TX2 eDP_TX2 A73 A74 LVDS_A1 LVDS_A1 eDP_TX1 eDP_TX1 A75 A76 LVDS_A2 LVDS_A2 eDP_TX0 eDP_TX...

Page 26: ...nnel A differential pairs O LVDS LVDS_A_CK LVDS_A_CK A81 A82 LVDS Channel A differential clock O LVDS LVDS_VDD_EN A77 LVDS panel power enable O 3 3V PD 100K LVDS_BKLT_EN B79 LVDS panel backlight enabl...

Page 27: ...P differential pairs O PCIE AC coupled off module eDP_VDD_EN A77 eDP power enable O 3 3V PD 100K eDP_BKLT_EN B79 eDP backlight enable O 3 3V PD 100K eDP_BKLT_CTRL B83 eDP backlight brightness control...

Page 28: ...R5 DDI0_PAIR5 B91 B92 DDI0_PAIR6 DDI0_PAIR6 B93 B94 DDI0_HPD B89 DP0_HPD HDMI0_HPD DDI0_CTRLCLK_AUX B98 DP0_AUX HMDI0_CTRLCLK DDI0_CTRLCLK_AUX B99 DP0_AUX HMDI0_CTRLDATA DDI0_DDC_AUX_SEL B95 DDI0_DDC_...

Page 29: ...Unplug and notification of the link layer I 3 3V PD 100K Module must tolerate high level in stand by mode The carrier board shall include a blocking FET on DP1_HPD to prevent back drive current from d...

Page 30: ...shall be placed on the Carrier TMDS0_CLK TMDS0_CLK B81 B82 HDMI Port Differential Pair Clock Lines HDMI0_HPD B89 Detection of Hot Plug Unplug and notification of the link layer I 3 3V PD 100K HDMI0_C...

Page 31: ..._LINK1000 A5 Gigabit Ethernet Controller 0 1000Mbit sec link indicator active low OD 3 3VSB PU TBD LED behaviour is TBC GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1 and 2 magn...

Page 32: ...l 0 Receive Input differential pair I SATA AC coupled on Module SATA1_TX SATA1_TX B16 B17 Serial ATA channel 1 Transmit Output differential pair O SATA AC coupled on Module SATA1_RX SATA1_RX B19 B20 S...

Page 33: ...IE_RX1 PCIE_RX1 B64 B65 PCI Express channel 1 Receive Input differential pair I PCIE AC coupled off Module PCIE_TX2 PCIE_TX2 A61 A62 PCI Express channel 2 Transmit Output differential pair O PCIE AC c...

Page 34: ...nanoX EL User s Guide PICMG COM 0 R3 0 Page 34 Copyright 2021 ADLINK Technology Inc 4 3 6 1 PCH HSIO Lane Assignments Name HSIO name on SOC Comment PCIE0 HSIO 2 PCIE1 HSIO 3 PCIE2 HSIO 4 PCIE3 HSIO 5...

Page 35: ...ed address command and data bus I O 3 3VSB LPC_FRAME B3 LPC frame indicates the start of an LPC cycle O 3 3VSB LPC_DRQ0 LPC_DRQ1 B8 B9 LPC serial DMA request I 3 3V Not connected LPC_SERIRQ A50 LPC se...

Page 36: ...data pairs for Port 5 I O 3 3VSB USB 1 1 2 0 compliant USB7 USB7 B37 B37 USB differential data pairs for Port 6 I O 3 3VSB USB 1 1 2 0 compliant USB_0_1_OC B44 USB over current sense USB ports 0 and...

Page 37: ...n USB0 I PCIE AC coupled off module USB_SSTX0 USB_SSTX0 B22 B23 Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB0 O PCIE AC coupled on module USB_SSRX1 USB_SSRX1 A...

Page 38: ...94 Clock from module to carrier board SPI BIOS flash O 3 3VSB SPI_POWER A91 Power supply for Carrier Board SPI sourced from Module nominally 3 3V The Module shall provide a minimum of 100mA on SPI_POW...

Page 39: ...TRIP A35 Active low output indicating that the CPU has entered thermal shutdown O 3 3V PU 10K 3 3V FAN_PWMOUT B101 Fan speed control Uses the Pulse Width Modulation PWM technique to control the fan s...

Page 40: ...nt Bus Alert active low input can be used to generate an SMI System Management Interrupt or to wake the system Power sourced through 3 3V standby rail and main power rails I 3 3VSB PU 10K 3 3VSB Note...

Page 41: ...3V PD 10K 3 3V After hardware RESET output low GPI 0 A54 General purpose input pins Pulled high internally on the module I 3 3V PU 10K 3 3V GPI 1 A63 General purpose input pins Pulled high internally...

Page 42: ...shall be PD on carrier board SER0_RX A99 General purpose serial port receiver I CMOS 3 3V PU 47K 3 3V Power rail tolerance 5V 12V SER1_TX A101 General purpose serial port transmitter O CMOS 3 3V Power...

Page 43: ...Should have weak pull up SUS_STAT B18 Indicates imminent suspend operation used to notify LPC devices O 3 3VSB SUS_S3 A15 Indicates system is in Suspend to RAM state Active low output An inverted cop...

Page 44: ...sed P 4 75 20 V VCC_5V_SBY B84 B85 B86 B87 Standby power input 5 0V nominal If VCC5_SBY is used all available VCC_5V_SBY pins on the connector s shall be used Only used for standby and suspend functio...

Page 45: ...tures This chapter describes connectors LEDs switches and additional items located on the module and not necessarily included in the PICMG standard spec ification The locations of these items are as b...

Page 46: ...is particularly useful during carrier design and bring up phase It offers access to the following critical parts of the module Test points measurement of internal power rails I2C bus for BIOS POST co...

Page 47: ...Codes below LED2 Green Power Source 3Vcc S0 LED ON S3 S4 S5 LED OFF ECO mode LED OFF LED3 Red BMC output and same signal as WDT B27 on BtB connector Module power up WD LED LED OFF Watchdog counting WD...

Page 48: ...OERROR 2 NO_SUSCLK 3 NO_SLP_S5 4 NO_SLP_S4 5 NO_SLP_S3 6 BIOS_FAIL 7 RESET_FAIL 8 RESETIN_FAIL 9 NO_CB_PWROK 10 CRITICAL_TEMP 11 POWER_FAIL 12 VOLTAGE_FAIL 13 RSMRST_FAIL 14 NO_VDDQ_PG 15 NO_V1P05A_PG...

Page 49: ...MG mode a BIOS chip cannot be placed in the SPI0 slot on the carrier In dual BIOS Failsafe mode both BIOS chips on the module are configured as SPI1 Only one of the two is connected to the SPI bus at...

Page 50: ...task the system is currently executing Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre boot process on production hardware A b...

Page 51: ...e 51 Copyright 2021 ADLINK Technology Inc 7 Software Support 7 1 1 Windows 10 IOT Enterprise 64 bit 7 1 2 Yocto Linux 64 bit https github com ADLINK meta adlink x86 64bit 7 1 3 Ubuntu Under planning T...

Page 52: ...8 Mechanical and Thermal 8 1 Module Dimensions Figure 5 Module mechanical dimensions All dimensions are shown in millimeters Tolerances should be 0 25mm unless otherwise noted The tolerances on the m...

Page 53: ...4 24 4 11 7 0 1 4 3 B A A A A B B B A M2 5 threaded through x4 B M3 0 threaded through x4 26 4 57 4 20 4 25 4 4 5 0 Hair line direction 8 2 Thermal Solutions 8 2 1 Heatspreader Bottom Mount HTS nXEL B...

Page 54: ...ight 2021 ADLINK Technology Inc A M2 5 threaded through x4 8 2 2 Heatsink High Profile Bottom Mount THSH nXEL B I High profile heatsink with threaded standoffs for bottom mounting Figure 7 Heatsink Hi...

Page 55: ...pyright 2021 ADLINK Technology Inc A M2 5 threaded through x4 8 2 3 Heatsink Low Profile Bottom Mount THS nXEL B I Low profile heatsink with threaded standoffs for bottom mounting Figure 8 Heatsink Lo...

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