nanoX-EL User’s Guide
PICMG COM.0 R3.0
Page 17
Copyright © 2021 ADLINK Technology, Inc.
3.
Block Diagram
BIOS
C
AB
6th Generation
Intel Atom® x6000E
Processor
(“Elkhart Lake”)
eDP to LVDS
eDP
build option, eDP 4 lanes
2 SATA 6Gb/s
Embedded Controller
SGMII
LAN PHY
(GPY 215, 211)
DDI 0
eDP/LVDS
USB 3.0 Lane 0-1
USB 2.0 Lane 0-7
SATA Port 0-1
Max. 2.5GbE
PCIe Lane 0-3
HDA
SPI
SMBus
I2C
GPIO/SDIO
UART 0-1/CAN
LPC/eSPI
2 USB 3.0
4 PCIe Gen3
x4, x2, x1 config.
eSPI
build option
eMMC 5.1
16GB-64GB
build option
eSPI to LPC
I2C
SDIO 3.0
HSUART
Thermal
sensor
(SOC)
Thermal
sensor
(board)
LPDDR4
16/32Gb
LPDDR4
16/32Gb
LPDDR4
16/32Gb
LPDDR4
16/32Gb
TPM 2.0
BIOS
Note: Maximum supported memory configuration shown
Figure 1 – Module function diagram
