34
•
Operation Theory
(PSC_Count er=2, retrig_no=3)
Acquisition_in_progress
Scan_start
ADCONV
Acquired & stored data
(6 scans)
Operation start
Trigger
Post Scan Count
2
1
0
1
0
1
0
2
2
Figure 18: Post trigger with re-trigger
4.1.4.3 Bus-mastering DMA Data Transfer
PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize
the maximum PCI bandwidth. The bus -mastering controller, which is built
in the PLX IOP-480 PCI controller, controls the PCI bus when it becomes
the master of the bus. Bus mastering reduces the size of the on-board
memory and reduces the CPU loading because data is directly transferred
to the computer’s memory without host CPU intervention.
Bus-mastering DMA provides the fastest data transfer rate on PCI-bus.
Once the analog input operation starts, control returns to your program.
The hardware temporarily stores the acquired data in the on-board AD
Data FIFO and then transfers the data to a user-defined DMA buffer
memory in the computer. Please note that even when the acquired data
length is less than the Data FIFO, the AD data will not be kept in the Data
FIFO but directly transferred into host memory by the bus-mastering DMA.
The DMA transfer mode is very complex to program. We recommend using
a high-level program library to configure this card. If users would like to
know more about programs/software’s that can handle the DMA bus
master data transfer, please refer to http://www.plxtech.com for more in-
formation on PCI controllers.
By using a high-level programming library for high speed DMA data ac-
quisition, users simply need to assign the sampling period and the number
of conversion into their specified counters. After the AD trigger condition is
matched, the data will be transferred to the system memory by the
bus -mastering DMA.
The PCI controller also supports the function of scatter/gather bus mas-
tering DMA, which helps the users to transfer large amounts of data by
linking all the memory blocks into a continuous linked list.
