ADLINK Technology cPCI-7300A User Manual Download Page 6

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4 Operation Theory .............................................................. 33

4.1

I/O Configuration................................................................ 34

4.2

Block Diagram.................................................................... 35

4.3

Digital I/O Data Flow .......................................................... 36

4.4

Input FIFO and Output FIFO.............................................. 37

4.5

Bus-mastering DMA........................................................... 38

4.6

Scatter/gather DMA ........................................................... 40

4.7

Clocking Mode ................................................................... 41

4.8

Starting Mode..................................................................... 43

4.9

Active Terminator............................................................... 44

4.10 Digital Input Operation Mode ............................................. 45

Digital Input DMA in Internal Clock Mode  ..................... 45
Digital Input DMA in External Clock Mode  .................... 47
Digital Input DMA in Handshaking Mode  ...................... 49
Continuous Digital Input ................................................ 51

4.11 Digital Output Operation Mode .......................................... 53

Digital Output DMA in Internal Clock Mode  .................. 53
Digital Output DMA in Handshaking Mode  ................... 54
Digital Output DMA in Burst Handshaking Mode  .......... 56
Pattern Generator  ......................................................... 59

4.12 Auxiliary DIO ...................................................................... 60

5 C/C++ Libraries ................................................................. 61

5.1

Libraries Installation ........................................................... 62

5.2

Programming Guide........................................................... 63

5.3

_7300_Initial ...................................................................... 64

5.4

_7300_Close...................................................................... 66

5.5

_7300_Configure ............................................................... 67

5.6

_7300_DI_Mode ................................................................ 69

5.7

_7300_DO_Mode............................................................... 70

5.8

_7300_AUX_DI .................................................................. 72

5.9

_7300_AUX_DI_Channel................................................... 73

Summary of Contents for cPCI-7300A

Page 1: ...Advance Technologies Automate the World Manual Rev 2 50 Revision Date July 1 2008 Part No 50 11106 1030 PCI PCIe cPCI 7300A 80 MB Ultra High Speed 32 CH Digital I O Boards User s Manual...

Page 2: ...or inability to use the product or documentation even if advised of the possibility of such damages This document contains proprietary information protected by copy right All rights are reserved No pa...

Page 3: ...ice adlinktech com TEL 886 2 82265877 FAX 886 2 82265717 Address 9F No 166 Jian Yi Road Chungho City Taipei 235 Taiwan Please email or FAX this completed service form for prompt and satisfactory servi...

Page 4: ......

Page 5: ...Outline 13 2 6 Connector Pin Assignment 14 2 7 Wiring and Termination 17 2 8 Termination Board Support 18 Connect with DIN 100S 18 Connect with DIN 502S 18 3 Registers 19 3 1 I O Port Base Address 20...

Page 6: ...gital Output Operation Mode 53 Digital Output DMA in Internal Clock Mode 53 Digital Output DMA in Handshaking Mode 54 Digital Output DMA in Burst Handshaking Mode 56 Pattern Generator 59 4 12 Auxiliar...

Page 7: ...t 88 5 21 _7300_DO_PG_Start 89 5 22 _7300_DO_PG_Stop 91 5 23 _7300_DI_Timer 92 5 24 _7300_DO_Timer 93 5 25 _7300_Int_Timer 94 5 26 _7300_Get_Sample 95 5 27 _7300_Set_Sample 96 5 28 _7300_GetUnderrunSt...

Page 8: ...iv List of Tables List of Tables Table 2 1 Connector Pin Assignment 14 Table 3 1 I O Port Base Address 20 Table 4 1 I O Configuration 34 Table 5 1 Data Types 63...

Page 9: ...low of digital input 36 Figure 4 3 Data flow of digital output 36 Figure 4 4 Maximum data throughput 38 Figure 4 5 Scatter gather DMA for digital output 40 Figure 4 6 Timer configuration 41 Figure 4 7...

Page 10: ...vi List of Figures...

Page 11: ...ured as two ports PORTA and PORTB each port controls 16 digital I O lines The I O can config ure as either input or output and 8 bit or 16 bit According to out side device environment users can config...

Page 12: ...cards provide the following advanced features X 32 digital input output channels X Extra 4 bit TTL digital input and output channels X Transfer up to 80M Bytes per second X SCSI active terminator for...

Page 13: ...nput Voltage X Low Min 0V Max 0 8 V X High Min 2 0 V Input Load X Terminator OFF Z Low 0 5 V 20 mA Z High 2 7 V 1 mA max X Terminator ON Z Termination resistor 110 Ohms Z Termination voltage 2 9V Z Lo...

Page 14: ...Bytes sec 32 bit input 20 MHz Programmable Counter X Device 82C54 10 X Digital Input Pacer 20 MHz 10 MHz or clock output of Timer 0 X Digital Output Pacer 20 MHz 10 MHz or clock output of Timer 1 Gene...

Page 15: ...typical onboard terminator on PCIe 7300A Z 12 V 119 mA typical onboard terminator off 287 mA typical onboard terminator on Z 3 3 V 499 mA typical onboard terminator off 543 mA typical onboard terminat...

Page 16: ...the func tions descriptions are included in this user s guide X Windows 95 DLL For VB VC Delphi BC5 the functions descriptions are included in this user s guide X PCIS DASK Include device drivers and...

Page 17: ...EE drivers are free shipped with the board You can install and use them without license For detail information about PCIS VEE please refer to the user s guide in the CD Manual Software Package PCIS VE...

Page 18: ...8 Introduction...

Page 19: ...d with automatic config uration the resource allocation is managed by the system BIOS Upon system power on the internal configuration registers on the board interact with the BIOS 2 1 What You Have In...

Page 20: ...n a grounded anti static surface component side up Again inspect the module for damage Press down on all the sock eted IC s to make sure that they are properly seated Do this only with the module plac...

Page 21: ...Installation 11 2 4 cPCI PCI PCIe 7300A Layout Figure 2 1 PCI 7300A Layout Diagram...

Page 22: ...12 Installation Figure 2 2 cPCI 7300A Layout Diagram Figure 2 3 PCIe 7300A Layout Diagram 167 65 111 15...

Page 23: ...by board basis It is not suggested to assign the system resource by any other methods PCI cPCI PCIe slot selection Please note that the PCI cPCI PCIe slot must provide bus mastering capability to ope...

Page 24: ...OL O Request line In handshaking mode DOREQ carries handshaking control information to peripheral 69 DOTRIG CONTROL I DO TRIG can be used to control the start of data output in all DO modes and to con...

Page 25: ...quisition in all DI modes 78 81 AUXDI3 0 DATA I AUX DI 3 0 can be used as extra input data or can be used as extra con trol signals 74 77 TERMPWR POWER TERMPWR 4 7V active terminator power output Pins...

Page 26: ...16 Installation Figure 2 4 CN1 Pin Assignment...

Page 27: ...t is important to terminate your cable properly to reduce or eliminate signal reflections in the cable The PCI cPCI PCIe 7300A support active terminator on board you can enable or disable the terminat...

Page 28: ...7300A It is suitable for the applications of 32 bit digital input or 32 bit digital output 2 8 2 Connect with DIN 502S The DIN 502S with the cable ACL 10252 separates the 100 pin SCSI connector into t...

Page 29: ...Configuration Registers PCR Local Configuration Registers LCR and cPCI PCI PCIe 7300A s regis ters The PCR which compliant to the PCI bus specifications is initial ized and controlled by the plug pla...

Page 30: ...ts Users should access these registers by 32 bits I O instructions The cPCI PCI PCIe 7300A occupies 8 consecutive 32 bit I O addresses in the I O address space Table 3 1 shows the I O Map of the cPCI...

Page 31: ...digital I O port X INT_CSR Interrupt control and status register X DI_FIFO DI FIFO direct access port X DO_FIFO DO FIFO direct access port X FIFO_CR FIFO almost empty full programming register X POL_...

Page 32: ...trol signals are disabled DI_CLK_SEL R W X 00 use timer0 output as input clock X 01 use 20MHz clock as input clock X 10 use 10MHz clock as input clock X 11 use external clock DI_REQ as input clock DI_...

Page 33: ...PORTB are configured as inputs both FIFO will be cleared Always get 0 when read DI_OVER R W X 0 DI FIFO does not full during input sampling X 1 DI FIFO full during input sampling some input data was l...

Page 34: ...disabled DO_MODE R W X 00 use timer1 output as output clock X 01 use 20MHz clock as output clock X 10 use 10MHz clock as output clock X 11 REQ ACK handshaking mode DO_WAIT_NAE R W X 0 do not wait outp...

Page 35: ...fect X 1 Clear digital output FIFO If both PORTA and PORTB are configured as outputs both FIFO will be cleared Always get 0 when read DI_UNDER R W X 0 DO FIFO does not empty during data output X 1 DO...

Page 36: ...ute READ WRITE Data Format This auxiliary digital I O is controlled by porgram I O only DO_AUX_3 DO_AUX_0 R W 4 bit auxiliary output port Program I O only DI_AUX_3 DI_AUX_0 R 4 bit auxiliary input por...

Page 37: ...UXDI0 interrupt X 1 Interrupt CPU on falling edge of AUXDI0 T2_EN R W X 0 Disable Timer2 interrupt X 1 Interrupt CPU on falling edge of Timer 2 output AUXDI0_INT R W X 0 AUXDI does not generate interr...

Page 38: ...igital input FIFO if the digital input is configured as 16 bit wide or 32 bit wide DI_FIFO_32 Bit 31 Bit 16 of digital input FIFO if the digital input is config ured as 32 bit wide Note Although this...

Page 39: ...8 of digital output FIFO if the digital output is config ured as 16 bit wide or 32 bit wide DO_FIFO_32 Bit 31 Bit 16 of digital output FIFO of the digital output is con figured as 32 bit wide Note Al...

Page 40: ..._PAF WO Programmable almost empty full threshold of PORTB FIFO 2 consecutive writes are required to program PORTB FIFO Pro grammable almost empty threshold first PA_PAE_PAF WO Programmable almost empt...

Page 41: ...edge active DI_ACK_NEQ R W X 0 DI_ACK is rising edge active X 1 DI_ACK is falling edge active DI_TRG_NEQ R W X 0 DI_TRG is rising edge active X 1 DI_TRG is falling edge active DO_REQ_NEQ R W X 0 DO_RE...

Page 42: ...DMA Control Registers The registers of bus mastering DMA as well as the control and status registers of PCI bus interrupts are built in the PLX PCI 9080 ASIC Users can refer to the manual of PLX PCI...

Page 43: ...r provides the detailed operation information for the cPCI PCI PCIe 7300A including I O configuration block diagram input output FIFO bus mastering DMA scatter gather clocking mode starting mode termi...

Page 44: ...O16 DO31 PORTA control signals are disabled X DI0 input LSB DI31 input MSB X DO0 output LSB DO31 output MSB X LSB Least Significant Bit MSB Most Significant Bit Mode Channel Description DI32 PORTA DI0...

Page 45: ...t it can be set as terminated mode or non terminated mode PORTB 16 Digital I O Port it can be set as terminated mode or non terminated mode FIFO Two 16K words FIFO for digital I O data buffer AUX DO 3...

Page 46: ...put operation After the bus mastering DMA of the PCI Bridge transfers the output data to the output FIFO the cPCI PCI PCIe 7300A will output the data to the external devices in a pre assigned period F...

Page 47: ...e function _7300_GetOverrunStatus For digital output operation data is moved from system memory to the output FIFO by bus mastering DMA assume the data transfer rate is DO pre transfer rate Then the d...

Page 48: ...a throughput of the cPCI PCI PCIe 7300A is also limited by the data throughput of the bridge chipset North Bridge NB between PCI bus and system memory The typical data throughput of NB chipset is 120M...

Page 49: ...Operation Theory 39 hard disk rather than memory the bottleneck would be the data transfer rate of the hard disk driver...

Page 50: ...hout limiting by the fragment of small size memory Users can configure the linked list for the input DMA channel or the output DMA channel Figure 4 7 shows the linked list that is constructed by three...

Page 51: ...mable timer 82C54 There are three counters in 82C54 counter 0 is used to generate sampling clock for digital input counter 1 is used timer pacer for digital output and counter 2 is used for inter rupt...

Page 52: ...can control the data input from the cPCI PCI PCIe 7300A by asserting the DO ACK pin when it is ready to receive data The software driver functions of 5 6 and 5 7 are provided to setup the clocking mo...

Page 53: ...trigger signal DI TRIG for digital input DO TRIG for dig ital output is activated 3 WaitFIFO This starting mode is only available for digital output The data transfer is started until the output FIFO...

Page 54: ...ble The PCI cPCI PCIe 7300A support active terminator on board you can enable or disable the terminator by software selection The active terminator is the same as the one used in SCSI 2 When the termi...

Page 55: ...ital input with internal clock are listed as follows 1 Define the input configuration to be 32 bit 16 bit or 8 bit data width 2 Enable or disable the active terminators 3 Define the input sampling rat...

Page 56: ...ternal device to the FIFO on board is higher than that from FIFO to system memory or the PCI bus is busy for a long time the FIFO become full and overrun situation occurs after the next data being wri...

Page 57: ...external clock are listed 1 Define the input configuration to be 32 bit 16 bit or 8 bit data width 2 Enable or disable the active terminators 3 Define the input sampling rate as external clock Con ne...

Page 58: ...operation flow is show as below The followings are timing diagrams of the DI REQ and the input data The active edge of DI REQ can be programmed by the func tion 5 5 Figure 4 7 DIREQ as input data str...

Page 59: ...30Mhz typically from PCI bus to system memory Users should check the overrun status when the DMA block size is larger than 16K samples If overrun al ways happens users should reduce the DMA block size...

Page 60: ...e starting mode to be NoWait or WaitTRIG 5 After digital input data is ready on device side the peripheral device strobe data into the cPCI PCI PCIe 7300A by asserting a DIREQ signal 6 The DIREQ signa...

Page 61: ...eve the continuous digital input function in a high speed sampling rate In this case the input FIFO buffers the input data and waits for the next DMA to move the queued data to the system memory To av...

Page 62: ...ut it is rec ommended to execute your application programs in the non multitask operation system to reduce the latency time between two DMA transfers Note The latency time between two DMA transfers is...

Page 63: ...figuration to be 32 bit 16 bit or 8 bit data width 2 Enable or disable the active terminators 3 Define the output timer pacer rate to be 20MHz 10MHz or the output 82C54 timer 1 The timer pacer control...

Page 64: ...dicate the output operation to the external device The timing diagram of the DOREQ is shown as follows Figure 4 10 DOREQ as output data strobe 4 11 2 Digital Output DMA in Handshaking Mode For digital...

Page 65: ...andshaking signals of the external device to output pin DO REQ and input pin DO ACK 4 Define the starting mode to be NoWait WaitTRIG Wait FIFO or WaitBoth 5 Digital output data is moved from PC s syst...

Page 66: ...dvantage of handshaking mode which is reliable and the advantage of internal clock mode which is fast When using this mode the sender has to check the availability of receiver indicated by the DO ACK...

Page 67: ...de the timer pacer rate to be 20Mhz 10Mhz or the output of 82C54 timer 1 4 Connect the handshaking signals of the external device to output pin DO REQ and input pin DO ACK 5 Define the starting mode t...

Page 68: ...busy for a long time the FIFO become empty and under run situation occurs after the next data being read from the out put FIFO Users should check the under run status to see whether the under run occu...

Page 69: ...samples The operations sequence of pattern generator are listed 1 Define the input configuration to be 32 bit 16 bit or 8 bit data width 2 Enable or disable the active terminators 3 Define the output...

Page 70: ...iary DIO The cPCI PCI PCIe 7300A also includes four auxiliary digital inputs and four digital outputs which can be applied to achieve the simple I O functions Users can refer to the functions 5 8 5 11...

Page 71: ...criptions of the Windows 98 NT 2000 Vista DLL functions The function prototypes and some useful constants are defined in the header files LIB directory DOS and INCLUDE directory Win dows 95 For Window...

Page 72: ...t how to install the software libraries for DOS or Win dows 95 DLL or PCIS DASK for Windows 98 NT 2000 The device drivers and DLL functions of Windows 98 NT 2000 are included in the PCIS DASK Please r...

Page 73: ...indows 95 DLL driver e g W_7300_Initial Data Types We defined some data type in Pci_7300 h DOS and Acl_pci h Windows 95 These data types are used by NuDAQ Cards library We suggest you to use these dat...

Page 74: ...to be set up by the users Syntax Visual C C Windows 95 int W_7300_Initial int card_number int pcic_base_addr int lb_base_addr int irq_no int pci_master Visual C C Windows 95 W_7300_Initial ByVal card...

Page 75: ...l give an available interrupt number to this card automatically pci_master TRUE BIOS enabled PCI bus mastering FALSE BIOS did not enable PCI bus mastering Return Code NoError PCICardNumErr PCIBiosNotE...

Page 76: ...card Syntax Visual C C Windows 95 int W_7300_Close int card_number Visual Basic Windows 95 W_7300_Close ByVal card_number As Long As Long C C DOS int _7300_Close int card_number Argument card_number T...

Page 77: ...nt dio_config int term_cntrl int cntrl_pol Argument card_number The card number of the cPCI PCI PCIe 7300A card dio_config The port configuration DI32 input port is 32 bit wide PORTB is configured as...

Page 78: ...PCICardNotInitInvalidDIOConfigure 1 DIREQ DIREQ_POS DIREQ signal is rising edge active DIREQ_NEG DIREQ signal is falling edge active 2 DIACK DIACK_POS DIACK signal is rising edge active DIACK_NEG DIA...

Page 79: ...OS int _7300_DI_Mode int card_number int clk_mode int start_mode Argument card_number The card number of the cPCI PCI PCIe 7300A card clk_mode DI_CLK_TIMER use timer0 output as input clock DI_CLK_20M...

Page 80: ...int clk_mode int start_mode int fifo_threshold Argument card_number The card number of the cPCI PCI PCIe 7300A card clk_mode DO_CLK_TIMER use timer1 output as output clock DO_CLK_20M use 20MHz clock...

Page 81: ...ay output data until DOTRIG is active and FIFO is not almost empty fifo_threshold programmable almost empty threshold of both PORTB FIFO and PORTA FIFO if PORTA is set as output It is avaliavle only w...

Page 82: ...ows 95 int W_7300_AUX_DI int card_number int aux_di Visual Basic Windows 95 W_7300_AUX_DI ByVal card_number As Long aux_di As Long As Long C C DOS int _7300_AUX_DI int card_number int aux_di Argument...

Page 83: ...digital input port Syntax Visual C C Windows 95 int W_7300_AUX_DI_Channel int card_number int di_ch_no int aux_di Visual Basic Windows 95 W_7300_AUX_DI_Channel ByVal card_number As Long ByVal di_ch_no...

Page 84: ...ws 95 int W_7300_AUX_DI int card_number int do_data Visual Basic Windows 95 W_7300_AUX_DI ByVal card_number As Long ByVal do_data As Long As Long C C DOS int _7300_AUX_DI int card_number int do_data A...

Page 85: ...al C C Windows 95 int W_7300_AUX_DO_Channel int card_number int do_ch_no int do_data Visual Basic Windows 95 W_7300_AUX_DO_Channel ByVal card_number As Long ByVal do_ch_no As Long ByVal do_data As Lon...

Page 86: ...buf_size As Long memID As Long linearAddr As Long As Long Argument buf_size Bytes to allocate Please be careful the unit of this argument is BYTE not SAMPLE memID If the memory allocation is successf...

Page 87: ...95 envi ronment This function is only available in the Windows 95 version Syntax Visual C C Windows 95 int W_7300_Free_DMA_Mem HANDLE memID Visual Basic Windows 95 W_7300_Free_DMA_Mem ByVal memID As...

Page 88: ...lar to DMA Direct Mem ory Access transfers in a PC but is really PCI bus mastering It does not use an 8237 style DMA controller in the host com puter and therefore it is not blocked in 64K maximal gro...

Page 89: ...eration applies here such as a receiver which cannot accept the transfers higher priority devices requesting the PCI bus etc Remember that only one PCI initiator can have bus mastering at any one time...

Page 90: ...a memory ID for identifying the allocated DMA memory as well as the linear address of the DMA memory for user to access the data buffer DOS With non chaining mode this is the start address of the mem...

Page 91: ...operation still active after DMA trans fer complete 1 disable digital input operation immediately when DMA transfer complete Return Code NoError PCICardNumErr PCICardNotInit DMATransferNotAllowed Inva...

Page 92: ...I_DMA_Status int card_number int status Visual Basic Windows 95 W_7300_DI_DMA_Status ByVal card_number As Long status As Long As Long C C DOS int _7300_DI_DMA_Status int card_number int status Argumen...

Page 93: ...transfer operation is stopped Syntax Visual C C Windows 95 int W_7300_DI_DMA_Abort int card_number Visual Basic Windows 95 W_7300_DI_DMA_Abort ByVal card_number As Long As Long C C DOS int _7300_DI_D...

Page 94: ...ituation occurs Using this function to check overrun status Syntax Visual C C Windows 95 int W_7300_GetOverrunStatus int card_number int overrun Visual Basic Windows 95 int W_7300_GetOverrunStatus ByV...

Page 95: ...al memID As Long ByVal count As Long As Long C C DOS int _7300_DO_DMA_Start int card_number U32 buff U32 count int repeat DMA_DSCR dma_dscr_ptr Argument card_number The card number of the cPCI PCI PCI...

Page 96: ...n chaining mode DMA transfer The digi tal output data is stored in buff 1 Use chaining mode DMA transfer The digital output data is stored in several buffers The information of the buffers is stored i...

Page 97: ...int W_7300_DO_DMA_Status int card_number int status Visual Basic Windows 95 W_7300_DO_DMA_Status ByVal card_number As Long status As Long As Long C C DOS int _7300_DO_DMA_Status int card_number int st...

Page 98: ...DO_DMA_Start function is stopped Syntax Visual C C Windows 95 int W_7300_DO_DMA_Abort int card_number Visual Basic Windows 95 W_7300_DO_DMA_Abort ByVal card_number As Long As Long C C DOS int _7300_DO...

Page 99: ...As Any ByVal count As Long As Long C C DOS int _7300_DO_PG_Start int card_number void buff_ptr U32 count Argument card_number The card number of the cPCI PCI PCIe 7300A card buff_ptr the start addres...

Page 100: ...90 C C Libraries BufNotDWordAlign DMADscrBadAlign...

Page 101: ...e _7300_DO_PG_Start function is stopped Syntax Visual C C Windows 95 int W_7300_DO_PG_Stop int card_number Visual Basic Windows 95 W_7300_DO_PG_Stop ByVal card_number As Long As Long C C DOS int _7300...

Page 102: ...DOS int _7300_DI_Timer int card_number U16 c0 Argument card_number The card number of the cPCI PCI PCIe 7300A card c0 frequency divider of Counter 0 Valid value ranges from 2 to 65535 Note Since the I...

Page 103: ...DOS int _7300_DO_Timer int card_number U16 c1 Argument card_number The card number of the cPCI PCI PCIe 7300A card c1 frequency divider of Counter 1 Valid value ranges from 2 to 65535 Note Since the...

Page 104: ...d_number U16 c2 Argument card_number The card number of the cPCI PCI PCIe 7300A card c2 frequency divider of Counter 2 Valid value ranges from 2 to 65535 Note Since the Integer type in Visual Basic is...

Page 105: ...index U32 data_value U32 portWidth Visual Basic Windows 95 W_7300_Get_Sample ByVal linearAddr As Long ByVal index As Long data_value As Long ByVal portWidth As Long As Long Argument linearAddr The li...

Page 106: ...U32 index U32 data_value U32 portWidth Visual Basic Windows 95 W_7300_Get_Sample ByVal linearAddr As Long ByVal index As Long ByVal data_value As Long ByVal portWidth As Long As Long Argument linearAd...

Page 107: ...ion to check underrun status Syntax Visual C C Windows 95 int W_7300_GetUnderrunStatus int card_number int underrun Visual Basic Windows 95 int W_7300_GetUnderrunStatus ByVal card_number As Long under...

Page 108: ...98 C C Libraries...

Page 109: ...or the 8254 in microprocessor based system are X programmable baud rate generator X event counter X binary rate multiplier X real time clock X digital one shot X motor control For more information abo...

Page 110: ...ting Bit 0 Note 1 The count of the binary counter is from 0 up to 65 535 Bit 7 6 5 4 3 2 1 0 SC1 SC0 RL1 RL0 M2 M1 M0 BCD SC1 SC0 COUNTER 0 0 0 0 1 1 1 0 2 1 1 ILLEGAL RL1 RL0 OPERATION 0 0 COUNTER LA...

Page 111: ...rrent counting 2 Write 2nd byte starts the new count Mode 1 Programmable One Shot The output will go low on the count following the rising edge of the gate input The output will go high on the termina...

Page 112: ...and the output is high the first clock pulse after the count is loaded decrements the count by 1 Subse quent clock pulses decrement the clock by 2 after time out the output goes low and the full count...

Page 113: ...the trig ger input and will go low for one clock period when the terminal count is reached The counter is re triggerable the output will not go low until the full count after the rising edge of any t...

Page 114: ...104 Appendix...

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