ADLINK Technology cPCI-7300A, User Manual

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Operation Theory 51
The following figure shows the timing requirement of the hand-
shaking mode digital input operation.
Figure 4-9: DIREQ & DIACK Handshaking
Note : DIREQ must be asserted until DIACK asserts, DIACK will be
asserted until DIREQ de-asserted.
4.10.4 Continuous Digital Input
If the digital input operation still active after the competition of the
previous DMA transfer and do not clear the data in the input FIFO
when the next DMA starts, the cPCI/PCI/PCIe-7300A can achieve
the continuous digital input function in a high-speed sampling rate.
In this case, the input FIFO buffers the input data and waits for the
next DMA to move the queued data to the system memory. To
avoid the overrun of input FIFO causes the data lost of the contin-
uous digital input, the latency time of the next DMA should be
smaller than the time to overrun the input FIFO. There are some
rules of thumb should be mentioned here:
1. The lower the sampling frequency is, the longer the time
to overrun the input FIFO is. That means the fewer over-
run situations will occur.
2. To reduce the latency time between two DMA transfers,
please disable unnecessary PCI bus mastering devices,