ADLINK Technology cPCI-6910 Series, User Manual

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70 Watchdog Timer
cPCI-6910 Series
The cPCI-6910’s custom watchdog timer circuit is integrated in the
Intel
®
6300ESB Southbridge.
The Intel
®
6300ESB ICH includes a two-stage Watchdog Timer
(WDT) that provides a resolution ranging from one microsecond to
ten minutes. The timer uses a 35-bit Down-Counter that is loaded
with the value from the first Preload register. The timer is then
enabled and starts to count down. The time at which the WDT first
starts counting down is called the first stage. If the host fails to
reload the WDT before the 35-bit down counter reaches zero, the
WDT generates an internal interrupt. After the interrupt is gener-
ated, the WDT loads the value from the second Preload register
into the WDT’s 35-bit Down-Counter and starts counting down.
The WDT is now in the second stage. If the host still fails to reload
the WDT before the second timeout, the WDT drives the
WDT_TOUT# pin low. The WDT_TOUT# pin is held low until the
system resets.
The WDT also supports free-running mode. Free-running mode is
a one stage timer that toggles the WDT_TOUT# after a program-
mable time.
Configuration Registers
The Intel
®
6300ESB ICH WDT appears as PCI Bus 0, Device 29,
Function 4 in the BIOS and has the standard set of PCI configura-
tion register. The configuration registers include:
Offset 10H: Base Address Register (BAR)
Determines the memory base for WDT down-counter setting.
This is used to set Preload value 1 register, Preload value 2
register, General Interrupt Status register, and Reload register.
Preload Value 1 & 2 registers
Holds the preload value for the WDT timer. This value is auto-
matically transferred to the down-counter every time the WDT
enters the first and second stages. Preload Value 1 register
locates at Base + 00H and Preload Value 2 register locates at
Base + 04H. Only bit [19:0] may be set. The register unlocking
sequence is necessary when writing to the Preload registers.