ADLINK Technology cPCI-6910 Series, User Manual

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20 Functional Description
cPCI-6910 Series
X Direct connection of two memory channel interfaces with
DDR2 400 DIMMs
X Full operational support in single-channel mode on either
channel interface. Lock-step support only for dual-channel
operation (logically shared address, independent data)
X Stacked or unstacked DIMM support for registered DDR2-
400 DIMMs
X 144-bit wide with ECC slot supports x72, registered DDR2
400 DIMMs in 256 MB/512 MB/1 GB package
X Maximum 16 GB support with DDR2 400 up to two stacked
DIMMs (1 GB x 4 DRAMs)
X Base DDR2 clock rates of up to 200 MHz
X Data interface double-pumped to 400 MHz
X Up to 3.2 GB/s (DDR2 400) data bandwidth per channel
X
S4EC/D4ED (144, 128) x 4, Intel
®
x4 Signal Device Data
Correction (x4 SDDC) ECC in dual-channel mode
X SEC/DED (72, 64) ECC on each channel when Intel
®
Sig-
nal Device Data Correction (SDDC) is disable
X 14-bit address bus
X RASUM fail-over to an on-line spare DIMM device
X Hardware refresh support for 100 MHz operation to facilitate
debug frequencies
X Memory mirroring
X ODT (on-die termination) for DDR2 400
X Four-channel DMA controller for embedded applications.
NOTE Refer to the Intel
®
E7520 Memory Controller Hub (MCH)
DMA Application Note. For additional details, contact
your local Intel field representative.