ADLINK Technology cPCI-3920 Series, User Manual

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Functional Description 25
PCI Express
The Intel 3100 Chipset provides one configurable x8 PCI
Express interface with a maximum theoretical bandwidth of 4
GByte/s. The x8 PCI Express interface may alternatively be
configured as two independent x4 PCI Express interfaces with
a maximum theoretical bandwidth of 2 GBytes/s each. The
Intel® 3100 Chipset also supports an additional x4 PCI
Express interface with a maximum theoretical bandwidth of 2
GBytes/s which may alternatively be configured as four inde-
pendent x1 PCI Express interfaces.
IICH
I/O Controller Hub (IICH) functions are integrated into the
Intel® 3100 Chipset, eliminating the requirement for a legacy
I/O bridge.
I/O Controller Hub Feature set comprises:
X
PCI Express Interface
X
Low Pin Count (LPC) Interface
X
Firmware Hub (FWH) Interface
X
Integrated Serial ATA (SATA) Host Controllers:
Z
Independent DMA operation on six ports
- Four ports in SATA 1.0a and AHCI mode
- Six ports in AHCI mode only
Z
Data transfer rates up to 150 Mbyte/s
X
Two controllers with up to four USB 2.0 ports:
Z
One EHCI USB 2.0 Host Controller to support a total of
four ports (shared with the UHCI ports)
Z
Two UHCI Host Controllers to support a total of four
ports (shared with the EHCI ports)
X
Interrupt Controller
X
Power Management Logic
X
DMA Controller
X
Timers Based on 82C54
X
High Precision Event Timers (HPET)
X
Real Time Clock with 256-byte Battery-backed CMOS RAM