ADLINK Technology Com Express nanoX-BT, User Manual

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nanoX-BT Page 29
4.4. XDP Debug Header
Optionally available on breakout PCB. The debug port is a connection into a target-system environment that provides
access to JTAG, run control, system control, and observation resources. The XDP target system connector is a Samtec
60-pin BSH-030-01 series connector. Specific plating types, locking clips, and alignment pin details of this connector
can be obtained from Samtec. No specific plating types, locking clips or alignment pins are required for the XDP tool.
Pin XDP Signal Target Signal I/O Device Pin XDP Signal Target Signal I/O Device
1 GND GND NA 2 GND GND NA
3 OBSFN_A0 TAP_PREQ# I/O SoC 4 OBSFN_C0 MCSI_GPIO[00] I SoC
5 OBSFN_A1 TAP_PRDY# I/O SoC 6 OBSFN_C1 GPIO_S5[22] I SoC
7 GND GND NA 8 GND GND NA
9 OBSDATA_A0 GPIO_S5[23] I/O SoC 10 OBSDATA_C0 GPIO_S0_NC[16] I/O SoC
11 OBSDATA_A1 GPIO_S5[24] I/O SoC 12 OBSDATA_C1 GPIO_S0_NC[17] I/O SoC
13 GND GND NA 14 GND GND NA
15 OBSDATA_A2 GPIO_S5[25] I/O SoC 16 OBSDATA_C2 GPIO_S0_NC[18] I/O SoC
17 OBSDATA_A3 GPIO_S5[26] I/O SoC 18 OBSDATA_C3 GPIO_S0_NC[19] I/O SoC
19 GND GND NA 20 GND GND NA
21 OBSFN_B0 OPEN 22 OBSFN_D0 OPEN
23 OBSFN_B1 OPEN 24 OBSFN_D1 OPEN
25 GND GND NA 26 GND GND NA
27 OBSDATA_B0 GPIO_S5[27] I/O SoC 28 OBSDATA_D0 GPIO_S0_NC[20] I SoC
29 OBSDATA_B1 GPIO_S5[28] I/O SoC 30 OBSDATA_D1 GPIO_S0_NC[21] I SoC
31 GND GND NA 32 GND GND NA
33 OBSDATA_B2 GPIO_S5[29] I/O SoC 34 OBSDATA_D2 GPIO_S0_NC[22] I/O SoC
35 OBSDATA_B3 GPIO_S5[30] I/O SoC 36 OBSDATA_D3 GPIO_S0_NC[23] I/O SoC
37 GND GND NA 38 GND GND NA
39 HOOK0 PMC_RSMRST# I SoC 40 ITPCLK/ HOOK4 Open NA
41 HOOK11 PMIC_PWRBTN# O System 42 ITPCLK#/ HOOK5 Open NA
43 VCC_OBS_AB V1P8A NA System 44 VCC_OBS_CD 1.8VS (Core) NA System
45 HOOK2 PMC_CORE_PW
ROK I SoC 46 HOOK6/ RESET# PMC_PLTRST# I SoC
47 HOOK3 ILB_RTC_TEST# O SoC 48 HOOK7/ DBR# PMC_RSTBTN# O SoC
49 GND GND NA 50 GND GND NA
51 SDA1 SDA I/O System 52 TDO TAP_TDO I SoC
53 SCL1 SCL I/O System 54 TRSTn TAP_TRST# O SoC
55 TCK1 Open NA 56 TDI TAP_TDI O SoC
57 TCK0 TAP_TCK O SoC 58 TMS TAP_TMS O SoC
59 GND GND NA 60 GND GND
(or XDP_PRESENT#
if required)
NA
Refer to the " Bay Trail M/D/I Platform” Debug Port Design Guide (DPDG), Document Number: 512816, Revision: 2.1