Active Technologies AT-1212, User Manual

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AT-1212 User Guide and Specifications - 15 - www.activetechnologies.it
Control/Indicator Description
START_CH Start the waveform generation
EN_CH0 Enable/disable the start on channel 1
EN_CH1 Enable/disable the start on channel 2
Trig Selection If Trig Selection is true, the global software trigger signal is
incoming from PXIe backplane (PXI_Trig0). It generates
the synchronized RUN for multiple modules.
If Trig Selection is false, the software trigger is incoming
from START_CH signal.
Trig Reset If Trig Reset is true, it resets the trigger(start) condition.
SysReset System reset
IO Module\lockedfast (indicator) If the indicator is true, the FPGA DCM has locked
IO Module\trig_out It sets the Trigger Out value
IO Module\trig_in(indicator) It reads the Trigger In value.
Write MEM CH0 / Write MEM CH1 If true, it writes the data contained into Write DATA
control at the address specified by Write Address into
CH0/CH1
Write DATA Memory data
Write Address Memory address
ClockSEL Select the clock source for DAC/OSerdes. If false, it selects
the Inst_DCM_CLOCK_DIV4 outputs; if true it selects the
Inst_PLL DCM clock outputs.
The user should set it to false if he needs to use the TCXO
onboard clock or set it to true if he needs to use the clock
coming from the Timing Board (PXIe backplane).
ClkEnable It enables the FPGA DCM clock output.
StartAddress1_CH0..StartAddress8_CH0
StartAddress1_CH1..StartAddress8_CH1
Start Address represents the starting pointer address of
the look-up tables.