Active Technologies AT-1212, User Manual

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AT-1212 User Guide and Specifications - 10 - www.activetechnologies.it
AT-1212 CLIP DESIGN
There are two DACs installed on the board that control the two available analog output channels.
The DAC contains two parallel LVDS input ports consisting of 14 differential LVDS signals DB[13:0].
Each data port runs internally at half the speed of the DAC Clock (1.25 GHz), so the user needs to
guarantee them the correct data rate.
The installed multiplexer selects the DAC clock source: it can be internal (from Clock Generator circuit
output) or external (from SMA connector).
The adapter module has a Clock Generator circuit that provides the 1.25 GHz clock to the DAC; the
clock generator source clock can be provided by 25 MHz onboard TCXO or by PXI_e DSTARA
backplane connection.
The uController write/read the DAC parameters, the Clock Gen registers and control the multiplexer
output. It performs also the Power up sequencing.
This CLIP provides read/write access to all FPGA look-up tables that are included in the project.
The data read from the look up tables are serialized by the CLIP to provide the requested data rate to
the DAC.
Clip files : AT_1212_IOModule_CLIP.xml; AT_1212_IOModule_CLIP.vhd; Inst_PLL_156M.vhd;
i2c_ctrl.vhd; OSerdes4_1.vhd; AT1212_Constraints.ucf; AT1212_IOModule.tbc