Actis VSBC-6872 Series, User Manual

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VSBC-6872 series
ACTIS Computer
36
3.15.8 VMEbus System Controller
The VSBC-6872 provides System Controller capabilities that can be enabled or disabled with the SLOT1
jumper. Please refer to
7.2 Board jumpers for jumper configuration.
The VSBC-6872 System Controller provides the following functions:
•
VMEbus Arbiter: SGL, PRI or RRS mode and programmable timeout.
- In SGL mode: Single Level, the arbiter uses only the BusRequest3 signal from VME and
activates only the BusGrant3 signal. The board with the higher relative priority is the nearest
to the slot1.
- In PRI mode: Prioritized, the arbiter uses the BusRequest3 as higher priority and
BusRequest0 as lower priority. If a master with higher priority requests the bus, a BCLR is
generated.
- In RRS mode: Round Robin Select, the level of the priority of the request lines change in a
circular manner. For example: If the Arbiter granted the bus to a Requester with level 2, the
next most higher level is the level 1, with all other level shifted respectively in the level
priority.
•
VME Bus Timer: BTO(16 to 112), the timeout period can be programmed from 16
µ
s to 112
µ
s
(in 16
µ
s increment).
•
IACK daisy-chain driver.
•
16 MHz system clock generator.
Please refer to the
VAM and XVCR registers description for more information.
3.15.9 Bridge DMA Controller
The 60x-to-VME bridge includes a 1-channel DMA controller to perform SRAM-to-VME and VME-to-
SRAM transfers without CPU utilization. A set of seven registers allows to configure and control DMA
transfers. The SRAM and VME start addresses are specified in two 16-bit registers for each. Each
address is split in high order and low order address registers. An 8-bit register specifies the data width
and VME cycle type of transfer; the address modifier code is automatically selected based on this register
setting. A 16-bit register specifies the length of transfer (the number of words to transfer) to transfer up to
256 kBytes in 4-byte (word) increment; it can be updated or not to reflect the progression of the DMA
transaction. A control and status register allows to start the DMA transaction after all other registers have
been set up. It is also possible to stop the transfer before completion. If enabled an interrupt is sent to the
host processor at the end of the DMA transaction. A status bit can be read to check that the transaction
completed without error.
Please refer to the
DMASAH , DMASAL , DMAVAH , DMAVAL , DMAVSS , DMASIZ , and DMACSR
registers description for more information.
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