Actis VSBC-6872 Series, User Manual

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43
VHM VME Interrupt Handler Mask Register
Address from MPC: CS4 + 0x1063
Address from VME: N/A
Access type: Read/Write
This register is used to mask incoming interrupt requests coming from the VMEbus. It selects which IRQ
lines are monitored by the VME Interrupt Handler.
8270 D8 D9 D10 D11 D12 D13 D14 D15
Value
x M7 M6 M5 M4 M3 M2 M1
Reset x 1 1 1 1 1 1 1
x: reserved, a one is returned when read
Name Description
Mx Interrupt Mask
0: IRQx is enabled
1: IRQx is masked
VHV VME Interrupt Handler: Vector Register
Address from MPC: CS4 + 0x1073 to CS4 + 0x107f
Address from VME: N/A
Access type: Read Only
Reading this register starts a VME Interrupt Acknowledge (IACK) cycle controlled by the bridge Interrupt
Handler. It then contains the status/ID returned by the acknowledged interrupter to the interrupt handler.
8270 D8 D9 D10 D11 D12 D13 D14 D15
Value
V7 V6 V5 V4 V3 V2 V1 V0
Reset
n/d n/d n/d n/d n/d n/d n/d n/d
n/d: not defined, is not determined by bridge at reset
Name Description
V(7..0) 8-bit status/ID read during IACK cycle
The offset used to access this register determines the level of interrupt to acknowledge:
VHV offset VME IRQ level to acknowledge
CS4 + 0x1073 1
CS4 + 0x1075 2
CS4 + 0x1077 3
CS4 + 0x1079 4
CS4 + 0x107b 5
CS4 + 0x107d 6
CS4 + 0x107f 7
An IACK cycle is started only when a VME interrupt is pending on the level
corresponding to the VHV offset accessed. In the case there is no pending
IRQ, no IACK cycle is started and value 0x00 is returned. Note that the VME
interrupt must not be masked to be acknowledged (report to VHM register
description).
Reading this register when there is no pending IRQ is not recommended.
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