Actis VSBC-6872 Series, User Manual

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User's guide
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3.15.4 VMEbus Requester
The VMEbus Requester is: RWD, ROR, FAIR, with programmable request level.
The requester requests the VMEbus as soon as the VME Master or the VME Interrupt Handler wants to
gain access of the bus. Its release mode (RWD or ROR) is defined in the VMBA register and its request
mode (FAIR) in the XVCR register.
A lock function set by VSBA24[VME_lock] tells the requester not to release the VMEbus in order to
provide the host processor with an exclusive VME access that may be required for a specific application.
Please refer to the
VMBA , XVCR , and VSBA24 registers description for more information.
3.15.5 VMEbus Interrupter
The VSBC-6872 can send any interrupt level to the VMEbus with its interrupter I(1-7), D08(O), ROAK.
Before generating this interrupt, the interrupt level and the vector must be defined with the VIVEC register
and/or VIL register.
The corresponding interrupt signal is asserted when writing any value to the VINTER register.
The interrupt is released at the end of the responding VME Interrupt Acknowledge (IACK) cycle.
Please refer to the
VIVEC , VIL , and VINTER registers description for more information.
3.15.6 VMEbus Interrupt Handler
The VSBC-6872 is VME Interrupt Handler IH(1-7), D08(O)
This interrupt-handler is able to recognize all IRQ VME levels.
All levels can be masked with the VHM register.
When an IRQ is coming from the VME side, an IRQ1 is sent to the MPC8270.
The user can then read the IRQ levels active in the VHIL register.
Depending on the IRQ level to be acknowledged, the user can read the vector in the corresponding offset
in the VHV register.
When reading the vector, a VME Interrupt Acknowledge (IACK) cycle is initiated.
Please refer to the
VHM , VHIL , and VHV registers description for more information.
3.15.7 VMEbus Mailbox
The VSBC-6872 provides a single Mailbox system. From the VME side, it is composed of a single
register: VSMAIL.
Before using this function, the VSBA24[MailOn] bit must be set to unmask the local IRQ.
When an external master writes to this register, an IRQ6 is sent to the host processor.
To clear this IRQ, the host processor must write any value to the VSMAIL register.
Please refer to the
VSMAIL and VSBA24 registers description for more information.
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