INDUSTRIAL I/O PACK SERIES AVME9675 VME64x 6U CARRIER BOARD
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4. Write “1” to the IP Interrupt Clear Register corresponding to the
desired IP interrupt request(s) being configured.
5. Write “1” to the IP Interrupt Enable Register bits corresponding
to the IP interrupt request to be enabled.
6. Enable interrupts from the carrier board by writing a "1" to bit 3
(global interrupt enable bit) in the Carrier Board Status Register.
Sequence of Events For an Interrupt
1. The IP asserts an interrupt request to the carrier board (asserts
IntReq0* or IntReq1*).
2. The AVME9675 carrier board acts as an interrupter in making
the VME64x bus interrupt request (asserts IRQx*)
corresponding to the IP interrupt request.
3. The VME64x bus host (interrupt handler) asserts IACK* and the
level of the interrupt it is seeking on A01-A03.
4. When the asserted VME64x bus IACKIN* signal (daisy-chained)
is passed to the AVME9675, the carrier board will check if the
level requested matches that specified by the host. If so, the
carrier board will assert the IntSel* line to the appropriate IP
together with (carrier board generated) address bit A1 to select
which interrupt request is being processed (A1 low corresponds
to IntReq0*; A1 high corresponds to IntReq1*).
5. The IP puts the appropriate interrupt vector on the local data bus
(D00-D07 if an D08 (O) interrupter or D00-D15 if a D16
interrupter), and asserts Ack* to the carrier board. The carrier
board passes this along to the VME64x bus (D08 [O] or D16)
and asserts DTACK*.
6. The host uses the vector to point at which interrupt handler to
execute and begins its execution.
7. Example of Generic Interrupt Handler Actions:
A. Disable the interrupting IP by writing a "0" to the appropriate
bit in the IP Interrupt Enable Register.
B. Take any IP specific action required to remove the interrupt
request at its source.
C. Clear the interrupting IP by writing a "1" to the appropriate
bit in the IP Interrupt Clear Register.
D. Enable the interrupting IP by writing a "1" to the appropriate
bit in the IP Interrupt Enable Register.
8. If the IP interrupt stimulus has been removed and no other IP
modules have interrupts pending, the interrupt cycle is
completed (i.e. the carrier board negates its interrupt request).
A. If the IP interrupt stimulus remains, a new interrupt request
will immediately follow. If the stimulus cannot be removed,
then the IP should be disabled or reconfigured.
B. If other IP modules have interrupts pending, then the
interrupt request (IRQx*) will remain asserted. This will
start a new interrupt cycle.
4.0 THEORY OF OPERATION
This section describes the basic functionality of the circuitry
used on the carrier board. Refer to the Block Diagram shown in the
Drawing 4501-802 as you review this material.
CARRIER BOARD OVERVIEW
The carrier board is a VME64x bus slave board providing up to
four industry standard IP module interfaces for the AVME9675. The
carrier board’s VME64x bus interface allows an intelligent single
board computer (VME64x bus Master) to control and communicate
with electronic devices that are external to the VME64x bus card
cage. The external electronic hardware may linked to the carrier
board rear access via a transition module (TRANS-200) or
proprietary interface. The electronic link from the field I/O
connections to the carrier board is made via the IP module selected
for your specific application.
To facilitate easy connection of external devices to the IP field
I/O pins of the carrier board, optional Termination Panels are
available. SCSI-2 cables connect a 50 pin IP field I/O connector on
the transition module (TRANS-200) to the Termination Panel. At the
Termination Panel field I/O signals are connected to a 50 position
terminal block via screw clamps. The AVME9675 contains up to
four IP modules, and thus 200 I/O connections may be provided via
the transition module through SCSI-2 connectors marked A-D.
•
The TRANS-200 was originally designed for use with the
AVME9670 product which supports four IP modules A-D. It is
also compatible with the AVME9675-4 (IP slots A-D) and
AVME9675-2 (IP slots A & B).
The VME64x bus and IP module logic commons have a direct
electrical connection (i.e., they are not electrically isolated).
However, the field I/O connections can be isolated from the VME64x
bus if an IP module that provides this isolation (between the logic
and field side) is utilized. A wide variety of IP modules are currently
available (from Acromag and other vendors) that allow interface to
many external devices for both digital and analog I/O applications.
VME64x bus Interface
The carrier board’s VME64x bus interface is used to program
and monitor the carrier board’s registers for configuration and control
of the board’s documented modes of operation (see section 3). In
addition, the VME64x bus interface is also used to communicate
with and control external devices that are connected to an IP
module’s field I/O signals (assuming an IP module is present on the
carrier board).
The VME64x bus interface is implemented in the logic of the
carrier board’s Field Programmable Gate-Array (FPGA). The FPGA
implements VME64x bus specification ANSI/VITA 1-1994 (VME64)
& ANSI/VITA 1.1-1997 (VME64x) as an interrupting slave including
the following data transfer types.
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A24, D16/D08(O) CR/CSR Register Space
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A16, D16/D08(O) Carrier Register Short I/O Access
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A16, D16/D08(O) IP Module ID Space
•
A16, D16/D08(EO) IP Module I/O Space
•
A24, D16/D08(EO) IP Module Memory Space
The carrier board’s VME64x bus data transfer rates are typically:
•
450ns for accesses to the carrier board registers.
•
450ns for data transfers to the IP modules (assuming 0 wait
states on IP).
The carrier board’s FPGA monitors the six geographical
address signal inputs supplied by the VME64x backplane on the P1
connector. These signals determine the base address of the carrier
in the standard (A24) Configuration ROM / Control & Status
Register (CR/CSR) address space. The host computer must scan
the CR/CSR space to determine active card locations within the
VME64x chassis. When the CR/CSR address matches the card’s,
the FPGA controls and implements the required bus transfer
allowing communication with the card’s CR/CSR space.
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