INDUSTRIAL I/O PACK SERIES AVME9675 VME64x 6U CARRIER BOARD
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Carrier Board Registers
The carrier board registers (presented in section 3) are
implemented in the logic of the carrier board’s FPGA. An outline of
the functions provided by the carrier board registers includes:
•
Configuration ROM (CR within CR/CSR space) registers
provide carrier board identification and capabilities information.
•
Control & Status Registers (CSR within CR/CSR space)
allow the base address of the Short (A16) I/O carrier space to
be relocated on 1K byte boundaries as desired by the host
computer using the Function 0 Address DEcoder CompaRe
(ADER) register and accesses to this space to be enabled or
disabled using the Bit Set or Bit Clear Registers.
The following registers are located in the carrier’s Short (A16)
I/O space:
•
Software reset can be issued to reset the FPGA Logic and all
IP modules present on the carrier board via the Status
Register.
•
Monitoring the error signal received from each IP module is
possible via the IP Error Register.
•
Configuration of VME64x bus A24 standard address space for
optional Memory Space on each IP module is possible.
Memory Space access to the IP modules can be individually
enabled via the IP Memory Enable Register. The base
address and address range (size) is programmed via carrier
registers IP_A and IP_B Memory Base Address & Size
Registers. The address size can be selected from 1M, 2M,
4M, or 8M bytes.
•
Enabling of VME64x bus interrupt requests from each IP
module via the IP Interrupt Enable Register is possible. The
desired VME64x bus interrupt level desired can be set (via the
Interrupt Level Register), and pending interrupts can be
monitored and cleared via carrier registers IP Interrupt
Pending and IP Interrupt Clear Registers.
•
Lastly, pending interrupts can be globally monitored and
released to the VME64x bus via the Status Register.
IP Logic Interface
The IP logic interface is also implemented within the carrier
board’s FPGA. The carrier board implements ANSI/VITA 4 1995 for
8 MHz operation only. Industrial I/O Pack logic interface
specification includes four IP logic interfaces on an AVME9675.
The VME64x bus address and data lines are linked to the address
and data of the IP logic interface. This link is implemented and
controlled by the carrier board’s FPGA.
The VME64x bus to IP logic interface link allows a VME64x bus
master to :
•
Access up to 32 ID Space bytes for IP module identification (ID
ROM Data Format I) via D08(O) data transfers using VME64x
bus A16 short address space.
•
Access up to 128 I/O Space bytes of IP data via D16/D08(EO)
data transfers using VME64x bus A16 short address space.
•
Access up to 8Mbytes of IP data mapped to Memory Space via
D16 or D08(EO) transfers using VME64x bus A24 standard
address space.
•
Respond to two IP module interrupt requests per IP with
software programmable VME64x bus interrupt levels.
Carrier Board Clock Circuitry
Separate 8MHz IP clocks are driven to each IP module. All
clock lines include series damping resistors to reduce clock
overshoot and undershoot, and similar length PC board trace
lengths are employed to minimize clock skew between the IP
modules.
IP Read and Write Cycle Timing
An IP read or write cycle is carried out via a VME64x bus A24 or
A16 data transfer. The data transfer starts when the VME64x bus
Data Strobe 0 (DS0*) goes active and ends when the carrier board
drives Data Transfer Acknowledge (DTACK*) active back to the
VME64x bus master. The carrier board typically has a 450ns IP
module data transfer cycle time.
A typical IP module data transfer cycle is described here,
starting with DS0* going active. DS0* is sampled on the rising edge
of the system 16MHz clock edge after it goes active. All operations
are then synchronized to the IP 8MHz clock as required by the IP
module specification. Thus, typically one 8MHz clock cycle later, an
IP select line goes active (IOSEL*, IDSEL*, MEMSEL*, or INTSEL*)
and is held active for one clock cycle. With no IP wait states, an
active IP Acknowledge (ACK*) signal is driven by the IP on the next
rising edge of the 8MHz clock. The carrier board samples ACK*
one clock cycle later and then asserts DTACK* ending the VME64x
bus data transfer.
Timing Diagram
CLK 16MHz
CLK 8mhz
DS0*
IOSEL*
ACK*
DTACK*
A Time-out error will result for the following condition if Auto
Acknowledge is disabled in the carrier status register.
If a select line (IOSEL*, IDSEL*, INTSEL*, or MEMSEL*) is
driven active to an IP module and the IP module does not return
ACK* active, then DTACK* will also not be generated by the carrier
board. This will cause a bus transfer time-out error and the VME64x
bus system may need to be reset. In addition, the carrier board will
remain in a state waiting for ACK* from the IP. To take it out of this
state, a software reset can be issued.
When an IP module places data on the bus, for all data read
cycles, any undriven data lines are read by the VME64x bus as high
because of pull-up resisters on the carrier board’s data bus.
VME64x bus Interrupter
Interrupts are initiated from an interrupting IP module. However,
the carrier board will only pass an interrupt generated by an IP
module to the VME64x bus if the carrier board has been first
enabled for interrupts. Each IP module can initiate two interrupts
which can be individually enabled on the carrier board. After
interrupts are enabled on the carrier board via the Interrupt Enable
Register (see section 3 for programming details), an IP generated
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