AP512 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 29 - http://www.acromag.com
- 29 -
https://www.acromag.com
Bits 5-
7 are only programmable when the EFR bit 4 is set to “1”. The
programmed values for these bits are latched when EFR bit 4 is cleared,
preventing existing software from inadvertently overwriting the extended
functions. A power-up or system reset sets all MCR bits to 0.
3.2.10 LSR - Line Status Register (Read/Write-Restricted)
The Line Status Register (LSR) provides status indication corresponding to
the data transfer. LSR bits 1-4 are the error conditions that produce
receiver line-status interrupts (a priority 1 interrupt in the Interrupt
Identification Register). The line status register may be written, but this is
intended for factory test and should be considered read-only by the
application software.
Table 3.11 Line Status
Register
LSR
Bit
FUNCTION
PROGRAMMING
0
Data Ready
(DR)
0 = Not Ready (reset low by CPU
Read of RHR or FIFO)
1 = Data Ready (set high when
character received and transferred
into the RHR or FIFO).
1
Overrun
Error (OE)
0 = No Error
1 = Indicates that data in the RHR is not being
read before the next character is transferred into
the RHR, overwriting the previous character. In
the FIFO mode, it is set after the FIFO is filled and
the next character is received. The overrun error
is detected by the CPU on the first LSR read after
it happens. The character in the shift register is
not transferred into the FIFO, but is overwritten.
This bit is reset low when the CPU reads the LSR.
2
Parity Error
(PE)
0 = No Error
1 = Parity Error - the received
character does not have the correct parity as
configured via LCR bits 3 & 4. This bit is set high
on detection of a parity error and reset low when
the host CPU reads the contents of the LSR. In
the FIFO mode, the parity error is associated with
a particular character in the FIFO (LSR Bit 2
reflects the error when the character is at the top
of the FIFO).
3
Framing
0 = No Error
