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26
Chapter 2
Advanced Chipset Features
Parameter
Description
Options
CAS Latency TIme
When synchronous DRAM is installed, the number of clock
cycles of CAS latency depends on the DRAM timing.
5,4,3,6,Auto
DRAM RAS# to CAS# Delay This field lets you insert a timing delay between the CAS
and RAS strobe signals, used when DRAM is written to,
read from, or refreshed, Fast gives faster performance; and
Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system.
2,3,4,5,6,Auto
DRAM RAS# Precharge
TIme
If an insufficient number of cycles is allowed for the RAS to
accumulate its charge before DRAM refresh, the refresh
may be incomplete and the DRAM may fail to retain data.
Fast fives faster performance; and Slow gives more stable
performance.This field applies only when synchronous
DRAM is installed in the syste.
2,3,4,5,6,Auto
Precharge Delay
This option is used to set up the timing delay between the
SDRAM active to precharge.
4,5,6,7,8,9,10,11,
12,Auto
On Chip Memory Size
Select the on chip memory size for VGA drive use.
PEG/Onchip VGA Control
This option is used to control the VGA
Onchip VGA
PEG Port
Auto
DVMT Mode
This option is used to select the video mode.
Fixed,DVMT,Both
DRAM Timing Selectable By SPD
x CAS Latency Time Auto
x DRAM RAS# Precharge Auto
F6:Load Optimized Defaults F7:Load Fail-Safe Defaults
PEG/Onchip VGA Control [Auto]
** VGA Setting **
X
On-chip Video Memory Size [Press Enter]
KLIJ
:Move Enter: Select +/-/ :Value ESC:Exit F1:General Help
DVMT Mode [DVMT]
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
x DRAM RAS# to CAS# Delay Auto
x Precharge delay (tRAS) Auto
SLP_S4# Assertion Width 4 to 5 Sec.
Help Item
Menu Level
X