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Chapter 2
PCI Latency Timer (CLK)
This item controls how long a PCI device can hold the PCI bus before another device takes over. Setting the
latency to longer periods enbles a PCI device to retain control of the bus longer before handing it over to another
device.
Maximum Payload Size
This BIOS feature determines the maximum TLP (Transaction Layer Packet) payload size that can be supported
by the motherboard chipset's PCI Express controller. The TLP payload size determines the amount of data
transmitted within each data packet. When set to 4096, the motherboard chipset's PCI Express controller supports
the maximum data payload of 4096 bytes within each TLP. This is the maximum payload size currently supported
by the PCI Express protocol.
Summary of Contents for Aspire AM3610
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Page 77: ...Chapter 3 71 19 Connect the USB cables 20 Connect the audio cable 21 Connect the SPDIF cable ...
Page 92: ...86 Chapter 3 19 Connect the USB cables 20 Connect the audio cable 21 Connect the SPDIF cable ...
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