ABACO VMIVME-1184 Series Hardware Reference Manual Download Page 36 | Manualshive

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Publication No. 500-001184-000 Rev. B.0

Programming 35

3.4.1 Interrupt Levels

These three bits (L2 through L0) set the interrupt level that the IP will present to
the host when a COS, or Marker request is made. The interrupt levels and the
field values are:

Bits 7 through 4: Marker Interrupt Enable and Level bits.
Bits 3 through 0: COS Interrupt Enable and Level bits.

The interrupt for the COS/SOE is cleared automatically when one of the following
conditions is met:

#1: ROAK mode - Interrupt Acknowledged
#2: ROFE mode - FIFO is emptied
#3: Interrupt enabled bit is cleared

The Quadrature Marker Pulse interrupt is cleared when its interrupt is
acknowledged, or when the MKR_INT_ENA bit is cleared.

3.5 Interrupt Processor COS Vector Register (Offset: $XXXX0D)

This is a read-write register, programmed by the user with the interrupt vector
value desired for the COS interrupt bits 7 through 0.

Default is $00

.

3.6 Interrupt Processor Marker Vector Register (Offset: $XXXX0E)

This is a read-write register, programmed by the user with the interrupt vector
value desired for the Marker interrupts bits 7 through 0.

Default is $00

.

3.7 Counter FIFO Register (Offset: $XXXX10)

This read-only 32-bit data register contains the value of the counter at the time
that the data capture was triggered. It should be read once with each read to the
Data register (two reads when used in SOE mode) so that time stamp/data
alignment will be maintained. This will result in the complete data structure as
shown:

In COS mode:

• Counter_Value

• COS_Input_Data

Setting Bit 9 in the CSR to one (1) enables this register.

In SOE mode, there are two data FIFO reads:

Table 3-8 Interrupt Level Bits

L2

L1

L0

IRQ Level

0

0

0

Disabled

0

0

1

IRQ1

0

1

0

IRQ2

0

1

1

IRQ3

1

0

0

IRQ4

1

0

1

IRQ5

1

1

0

IRQ6

1

1

1

IRQ7

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Summary of Contents for VMIVME-1184 Series

Page 1: ...tilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of their respective owners ...

Page 2: ...VMIVME 1184 32 bit Optically Isolated Change of State COS Input Board with Sequence of Events SOE Publication No 500 001184 000 Rev B 0 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 3: ...co Systems is registered with an approved Producer Compliance Scheme PCS and subject to suitable contractual arrangements being in place will ensure WEEE is processed in accordance with the requirements of the WEEE Directive Abaco Systems will evaluate requests to take back products purchased by our customers before August 13 2005 on a case by case basis A WEEE management fee may apply Artisan Tec...

Page 4: ...a hexadecimal number following the C programming language convention Thus One dozen 12D 0x0C 1100b The multipliers k M and G have their conventional scientific and engineering meanings of x103 x106 and x109 respectively The only exception to this is in the description of the size of memory areas when k M and G mean x210 x220 and x230 respectively NOTE When describing transfer rates k M and G mean ...

Page 5: ... to manuals via the website LINK www abaco com products Third party Documents For a detailed explanation of the VMEbus and its characteristics refer to ʺThe VMEbus Specificationʺ available from VITA VMEbus International Trade Association 7825 East Gelding Dr No 104 Scottsdale AZ 85260 602 951 8866 FAX 602 951 0720 www vita com NOTE Technical literature describing components used on the VME 1184 is...

Page 6: ...the state changes to detect by programming the Control and Status Register CSR1 and the COS Select register This board stores up to 512 state changes when the COS logic is enabled This prevents the board from losing a state change during interrupt servicing For SOE operation a maximum of 256 state changes are stored The board also supports byte word and longword data transfers during basic input d...

Page 7: ...le in byte word or longword accesses The board can be programmed to interrupt the system based on a change in the inputs Change of State COS circuitry monitors the logical state of the inputs When an input channel changes its state for example from a logic one to a logic zero and the COS logic is set to trigger on that event an interrupt can be issued to the host CPU The COS logic is programmed vi...

Page 8: ... Atmosphere Do not operate the system in the presence of flammable gases or fumes Operation of any electrical system in such an environment constitutes a safety hazard Keep Away from Live Circuits Operating personnel must not remove product covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power cable connected Unde...

Page 9: ...s Modifier Selection 22 2 4 3 Debounce Timing 24 2 5 Input Configurations 24 2 6 Connector Description 25 2 6 1 Barrier Terminal Transition Panels 25 3 Programming 29 3 1 Introduction 29 3 1 1 Board ID BD ID Register 30 3 2 Control and Status Registers 30 3 2 1 CSR1 Bit Definitions 30 3 2 2 CSR2 Bit Definitions 31 3 2 3 Counter Connectivity 32 3 2 4 Quadrature Counter Decoder Bits Bits 16 17 and 1...

Page 10: ...nable Register CH_INT_ENA 38 3 9 Firmware Revision Register FREV 38 3 10 Counter Feature 39 3 11 Counter Operation 39 3 11 1 CSR1_ 5 4 Definitions 39 3 11 2 2X Quadrature Mode 40 3 11 3 4X Quadrature Mode 41 3 12 Initialization 41 3 13 VMIVME 1184 Inputs 42 3 14 Marker Gating 43 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 11: ...1 4 Channel 31 Input Circuitry Channel 32 uses Vext 2 20 Figure 2 1 Switch and Jumper Locations 23 Figure 2 2 P1 P2 Connector Pin Layout 26 Figure 3 1 COS and SOE Registers 36 Figure 3 2 Leading Edge Example 40 Figure 3 3 1x Counter Mode 40 Figure 3 4 2x Counter Mode 40 Figure 3 5 2X Quadrature 40 Figure 3 6 4X Quadrature 41 Figure 3 7 Marker Gating Diagram 43 Artisan Technology Group Quality Inst...

Page 12: ...Register 2 Bit Map 31 Table 3 6 Data FIFO Register Bit Map 34 Table 3 7 Interrupt Processor Control Register Bit Map 34 Table 3 8 Interrupt Level Bits 35 Table 3 9 COS SEL B A 36 Table 3 10 COS Select Register 0 Bit Map 37 Table 3 11 COS Select Register 1 Bit Map 37 Table 3 12 COS Select Register 2 Bit Map 37 Table 3 13 COS Select Register 3 Bit Map 37 Table 3 14 FIFO Count Register Bit Map 38 Tab...

Page 13: ...coding logic and the data steering logic The register decoder selects which data register BD ID CSR IP or input is used during a data transfer The IP interface contains the logic to control the IP interfaces with the VMEbus and issues the interrupt request The COS logic controls the FIFO s data flow determines if a change of state has occurred and whether it is deemed an event and stored The input...

Page 14: ...upt Service Routine ISR on the VMEbus 1 2 VMEbus Interface The bus interface logic consists of bus signal buffers and transceivers that meet the VMEbus specification loading requirements The address decoder or board select logic can respond to standard 24 bit or short 16 bit data I O accesses The steering logic selects which VMEbus data lines to connect to the boardʹs Internal Data Bus IDB and whi...

Page 15: ...tch S29 When the decoder determines that the board is being accessed the VMEbus state is stored in a register and the BD_SEL lines are activated The board select line clocks the input registers and records the state of the external circuits The register decoder uses the bus state information to put the proper data on the IDB and to energize the VMEbus interface data transceivers The bus interface ...

Page 16: ... debounce clock is derived from the 16 MHz VMEbus system clock and is not intended as a synchronizing clock The debounce clock is started when a COS condition is detected This approach yields a lower latency with glitch reduction capability Debounce is used on inputs to reduce glitches false data transitions or noise Typically a state machine is used to transition with a clock of a particular rate...

Page 17: ...eration of the COS state machine A flagged Change Of State COS event occurs when one or more input channel s state changes in a way that the VMIVME 1184 has been programmed to detect For example if Channel 3 changes from a one 1 to a zero 0 and the COS Select Register has been programmed to detect falling edges for Channel 3 then Channel 3 causes a flagged COS event A non flagged COS event would o...

Page 18: ...onizing clock The debounce circuitry is another factor that can skew simultaneous events Consider a situation where two incoming signals are skewed by one or more synchronizing clock cycles the synchronized incoming signals can encounter another early late condition as was in the synchronizing clock with the debounce circuitry With the COS detection and FIFO circuitry running at the VMEbus clock r...

Page 19: ...er and system integrator should take this condition into consideration 1 6 Inputs The input circuit is easily configured by the user to be either Voltage Sensing or Contact Closure Figure 1 3 Channels 1 30 Input Circuitry on page 19 shows the circuitry for input channels 1 30 For monitoring circuits which short the inputs use the Contact Closure input circuit Otherwise use the Voltage Sensing circ...

Page 20: ...ure 1 4 Channel 31 Input Circuitry Channel 32 uses Vext 2 on page 20 inputs 31 and 32 can be sacrificed to provide two external voltages Vext1 and Vext2 to the pull up SIP resistors CAUTION User supplied voltages should not exceed 28V for normal operation Figure 1 3 Channels 1 30 Input Circuitry Table 1 3 Contact Closure SIP Resistors and Switch Assignments Channels SIP Resistor Socket Voltage Sou...

Page 21: ...Input Circuitry Channel 32 uses Vext 2 P2 A31 High P2 C31 Low Channel 31 TVS Rs1 Switch selectable Dp opto isolator Detection x8 SIP socketed Vbank EXT 1 Ext 2 12 5 For Contact Sensing Only Rup Rs2 Vext 1 Chassis GND OverVoltage Protection 60V Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 22: ...tic field When the board is placed on a bench for configuring etc it is suggested that conductive material should be placed under the board to provide a conductive shunt Unused boards should be stored in the same protective boxes in which they were shipped 2 3 Physical Installation CAUTION Do not install or remove the boards while power is applied 2 3 1 Before Applying Power Checklist Before insta...

Page 23: ...e address The values of these bits is determined by the switch position When a switch is ON the address bit value is zero ʺ0ʺ for a match If the switch is OFF the value is a one ʺ1ʺ Therefore turn each switch ON for every zero ʺ0ʺ in the base address of the board This board is designed to respond to standard A24 or short A16 address ranges S12 1 is used to establish the address range for the board...

Page 24: ...te Blaster 1 ON Terminate A ON Vext2 on pin A32 ON Vext1 on pin A31 CH 25 32 CH 17 24 CH 9 16 Differential Termination 2 ON Terminate B Switches 4 8 are unused CH 1 8 Supervisory NonPrilileged ALL Pos1 5V Pos2 12V Pos3 Vext1 Pos4 Vext2 Allowed Access Modes 28V 12V 5V 28V 12V 5V on on on 1 6 5 12 11 14 13 18 17 24 23 26 25 32 31 S2 1 2 4 1 2 4 1 2 4 1 2 4 on on S5 S4 S6 S8 S7 S9 S10 S11 CH29 30 CH2...

Page 25: ...or noisier switches and relays NOTE NOTE If no jumper is installed the debounce time will be set to 1μs Although the jumper setting is latched upon release of VMEbus SYSRESET the read write register setting can be changed through software later 2 5 Input Configurations The input circuitry of the VMIVME 1184 can be configured to monitor a variety of external circuits The user also has control over ...

Page 26: ...ee Figure 2 2 on page 26 for connector pinouts 2 6 1 Barrier Terminal Transition Panels The VMIVME 1184 can be used with Abaco s BT0X family of BT transitions panels The VMIACC BT01 02 03 and 04 family of BT transition panels meets ANSI IEEE SWC TEST The BT transition panels provides a passive breakout of the discrete wires of the ribbon cables allowing for a more efficient interface between exter...

Page 27: ...C3 VME_D 10 B3 N C A3 VME_D 2 C4 VME_D 11 B4 Tied to B5 A4 VME_D 3 C5 VME_D 12 B5 Tied to B4 A5 VME_D 4 C6 VME_D 13 B6 Tied to B7 A6 VME_D 5 ROW PIN 32 PIN 31 PIN 30 PIN 29 PIN 28 PIN 27 PIN 26 PIN 25 PIN 24 PIN 23 PIN 22 PIN 21 PIN 20 PIN 19 PIN 18 PIN 17 PIN 16 PIN 15 PIN 14 PIN 13 PIN 12 PIN 11 PIN 10 PIN 9 PIN 8 PIN 7 PIN 6 PIN 5 PIN 4 PIN 3 PIN 2 PIN 1 REAR VIEW OF BOARD A C B Artisan Technol...

Page 28: ...VME_D 10 B28 VME_IRQ 3 n A28 VME_A 3 C29 VME_D 9 B29 VME_IRQ 2 n A29 VME_A 2 C30 VME_D 8 B30 VME_IRQ 1 n A30 VME_A 1 C31 VCC_12 0 B31 N C A31 N C C32 VCC_5 0 B32 VCC_5 0 A32 VCC_5 0 Table 2 4 P2 Pin Assignments Pin Function Pin Function Pin Function C1 CH 1 INPUT B1 VCC_5 0 A1 CH 1 INPUT C2 CH 2 INPUT B2 GND A2 CH 2 INPUT C3 CH 3 INPUT B3 N C A3 CH 3 INPUT C4 CH 4 INPUT B4 N C A4 CH 4 INPUT C5 CH ...

Page 29: ...9 A28 CH 28 INPUT C29 CH 29 INPUT B29 VME_D 30 A29 CH 29 INPUT C30 CH 30 INPUT B30 VME_D 31 A30 CH 30 INPUT C31 CH 31 INPUT B31 GND A31 CH 31 INPUT C32 CH 32 INPUT B32 VCC_5 0 A32 CH 32 INPUT Table 2 4 P2 Pin Assignments Continued Pin Function Pin Function Pin Function LED Test 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CLOCK OUT CLOCK IN FAIL A Channel A...

Page 30: ...he VMEbus The FIFOs and the BD ID registers are read only The board s read only registers will not respond to writes and the data will be ignored During a read of the current Data registers the board will sample the data received at the input P2 and transfer that data to the VMEbus Most registers can be accessed using byte word or longword transfers The FIFO register CTR_FIFO and the QUAD_CTR can ...

Page 31: ... of State mode and to a one 1 for the Sequence of Events mode Default is 0 Bit 10 ROFE ROAK 0 1 Release interrupt on FIFO Empty Release Interrupt on Acknowledge Default is 0 Bit 09 EN CTR FIFO Bit 9 enables storage of the Counter value each time a COS or SOE event occurs Default is 0 24 CH_INT_ENA Channel Interrupt Enable register RW 28 DB_Data Debounced Data Register R 30 FREV Firmware Revision I...

Page 32: ...R2 Bit Definitions The Offset for the Control and Status Register is XXXX34 The term ʺgatingʺ means to qualify a signal For some encoders the marker pulse should be gated with the ʺAʺ or ʺBʺ channel in such a way as to qualify it The actual marker signal could be quite long in duration but it takes ʺAʺ and or ʺBʺ to be a certain state before the marker is actually considered valid Table 3 4 Correl...

Page 33: ...he connectivity status for all six wires is latched in as VME_SYSRESET goes away If a conflicting configuration is attempted this bit is set For example trying to use 2 channels without a ʺBʺ wire connected Also if a connectivity change occurs after RESET then this bit is set as a warning indication Writing a ʺ0ʺ to this bit forces a re read of the latest wire status and may clear the warning if i...

Page 34: ... Low CSR 1 and 2 are used to control the basic functions of the board The Fail LED is user controlled and can be turned off when the board is working properly Two bits of the CSR1 Bits 13 and 12 are used to monitor the COS memory device FIFO Bit 12 FIFO_Full and Bit 13 FIFO_Empty allow the user to monitor the current condition of the FIFO If a FIFO is full any new flagged data will be lost All bit...

Page 35: ... regardless of mode of operation COS 1 Read to capture the data SOE 2 Read to capture the data 3 4 Interrupt Processor Control Register This Read Write register is used to configure the operations of the Interrupt Processor Table 3 6 Data FIFO Register Bit Map FIFO Register Offset XXXX08 Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 Bit 23 Bit 22 B...

Page 36: ...ctor value desired for the COS interrupt bits 7 through 0 Default is 00 3 6 Interrupt Processor Marker Vector Register Offset XXXX0E This is a read write register programmed by the user with the interrupt vector value desired for the Marker interrupts bits 7 through 0 Default is 00 3 7 Counter FIFO Register Offset XXXX10 This read only 32 bit data register contains the value of the counter at the ...

Page 37: ...x These bits work as a pair for the stated channel They define the COS trigger condition for the associated channel Their states and functions are Example Setting Bits 15 and 14 of address XXXX1E will cause a COS trigger on any edge occurrence for channel 7 Table 3 9 COS SEL B A B A Function 00 No interrupts data only 01 Rising edge interrupts only 10 Falling edge interrupts only 11 Any edge inter...

Page 38: ...ister 0 Bit Map COS Select Register 0 XXXX18 Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 31B 31A 30B 30A 29B 29A 28B 28A Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 27B 27A 26B 26A 25B 25A 24B 24A Table 3 11 COS Select Register 1 Bit Map COS Select Register 0 XXXX1A Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 09 Bit 08 23B 23A 22B 22A 21B 21A 20B 20A Bit 07 Bit 06 Bit 05 ...

Page 39: ...r is a 32 bit read only register located at offset 30 It is accessible as byte word or longword For example if the firmware revision is 1 2 17 a read from the register is 00 01 02 17 Table 3 14 FIFO Count Register Bit Map FIFO_CNT Offset XXXX20 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 09 Bit 08 Bit 07 Bit 06 Bit 05 Bit 04 Bit 03 Bit 02 Bit 01 Bit 00 Table 3 15 Counter FIFO Count Register Bit ...

Page 40: ... equipment NOTE NOTE All three channels A B and M have a maximum input change rate of 100ns If changes on these channels occur faster then missed changes or counting errors may occur 3 11 Counter Operation Four counter modes are selected based on the resolution required by the application and the encoder used The VMIVME 1184 utilizes two simple incremental counter modes 1X and 2X and two quadratur...

Page 41: ... A This mode is set through CSR1 Bits 5 and 4 CRS1_ 5 1 CSR1_ 4 0 Figure 3 5 illustrates the relationship between inputs A and B and the count value in the 2X quadrature mode Figure 3 5 2X Quadrature A B A leading B example A B B leading A example All rising edges of A increment counter 1 2 3 A B Ignored in this mode Any edges of A increment counter 1 2 3 A B Ignored in this mode 4 2X Quadrature C...

Page 42: ... of what needs to be done in your program The descriptions assume an understanding of the VMEbus priority interrupt system The following is an example setup of the VMIVME 1184 Since each input channel is individually programmable regarding the type of transition that will trigger an event caution should be used We will program four inputs for each of the COS SOE operating modes We will configure C...

Page 43: ... and Marker interrupt enable bits have to be set One way is to write the entire byte of data again only this time with the enable bits set For this example the value to write would be AC Now the board will issue interrupts as the COS logic and Marker dictate 3 13 VMIVME 1184 Inputs Regardless of the wiring configuration single ended versus differential only channel A is used for counter modes whil...

Page 44: ... M A B Results Bits 5 4 3 2 1 0 0 X X 1 1 0 1 X 1 1 1 1 1 1 0 0 X X 0 1 1 0 0 1 Matches M input M gated with A M gated with both A and B Exact inverse of M input no gating M gated with the inverse of A and B X Don t Care Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 45: ...TIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO WARRANTIES OF DESIGN MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ALL OTHER LIABILITY ARISING FROM RELIANCE ON ANY INFORMATION CONTAINED HEREIN IS EXPRESSLY DISCLAIMED Abaco Systems Information Centers Americas 1 866 652 2226 866 OK ABACO or 1 256 880 0444 International Europe Middle East and Africa 44 0...

Page 46: ...quipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentation Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate representative or authorized distributor for any manufacturer listed herein We re here to make your life easier How...

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