Publication No. 500-001184-000 Rev. B.0
Theory of Operation 15
interrupts are enabled, a full FIFO will generate an interrupt with the same level
and vector as COS.
NOTE
If COS events come faster than the CPU can service, interrupt starvation will occur, keeping regular
programs from executing. Please keep this in mind when configuring your system. Be especially mindful
of completely emptying the FIFO(s) and limiting the capture of events to those which are actually
necessary for operation. You could easily setup a condition in which too many events are being stored
before an interrupt-generating event occurs..
1.3 Register Decoder
The register decoder uses the five lowest address lines and data strobes to select
which register is placed on the IDB. The decoder is used during any board access.
It uses a simple demultiplexer scheme. The address lines are decoded when the
board select lines are asserted. Based upon the address lines and the data strobes,
the proper register or registers are activated or clocked. A memory map showing
the relative addresses for each register is listed in
Chapter 3, Programming
of this
manual.
1.4 Debounce
The debounce clock is derived from the 16 MHz VMEbus system clock and is not
intended as a synchronizing clock. The debounce clock is started when a COS
condition is detected. This approach yields a lower latency with glitch-reduction
capability.
Debounce is used on inputs to reduce ‘glitches’, false data transitions or noise.
Typically, a state machine is used to transition with a clock of a particular rate or
frequency. If the data’s new state changes back, before two clock cycles, then that
transition is thrown away (the data is considered not to have changed) and the
input channel is resampled for any new changes.
All 32 data input channels are debounced (the debounce time is user-configurable
from 1µs to 10ms). None of the counter inputs are debounced in order to more
accurately track high-speed precision encoders, and to better handle an encoder
stopping on a transition when machine vibration causes small but high speed
movement back and forth across the same transition. The counter should never
accumulate, or lose counts when the encoder is simply vibrating.
NOTE
Although the counter inputs are not debounced, they do have a maximum input change rate of 100nsec.
If changes occur faster than 100nsec, then missed changes or counting errors may occur.
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