Aaeon GENE-EHL7 User Manual Download Page 85

Page: 85 / 119

Chapter 3

–

AMI BIOS Setup

3.5

” S

mp
act

ard

ENE

-E

Options Summary: "SMBUS"

Bit offset

Optimal Default, Failsafe Default

Fill bit offset for register, for robot to compare with bit value.
Bit value

Low

Optimal Default, Failsafe Default

High

Fill bit value for robot to compare register-bit with specified offset.
Byte value

Optimal Default, Failsafe Default

Fill a byte value for robot to compare register data with, in hexadecimal. Range: 0

–

FF.

Options Summary: "Legacy I/O"

I/O Address

Optimal Default, Failsafe Default

Fill I/O address device is responding to. Range: 0~FFFF.
Device

Is not

Optimal Default, Failsafe Default

Select that robot should or should not do action if condition met.
In condition

Present

Optimal Default, Failsafe Default

Specified register data

Summary of Contents for GENE-EHL7

Page 1: ...Last Updated September 26 2023 GENE EHL7 3 5 Subcompact Board User s Manual 1st Ed ...

Page 2: ...d in this manual is intended to be accurate and reliable However the original manufacturer assumes no responsibility for its use or for any infringements upon the rights of third parties that may result from its use The material in this document is for product information only and is subject to change without notice While reasonable efforts have been made in the preparation of this document to ass...

Page 3: ...leron are registered trademarks of Intel Corporation ITE is a trademark of Integrated Technology Express Inc IBM PC AT PS 2 and VGA are trademarks of International Business Machines Corporation Linux is the registered trademark of Linus Torvalds in the U S and other countries Ubuntu and Canonical are registered trademarks of Canonical Ltd All other product names or trademarks are properties of the...

Page 4: ...L7 Packing List Before setting up your product please make sure the following items have been shipped Item Quantity GENE EHL7 1 If any of these items are missing or damaged please contact your distributor or sales representative immediately ...

Page 5: ...d descriptions and explanations on the product s hardware and software features if any its specifications dimensions jumper connector settings definitions and driver installation instructions if any to facilitate users in setting up their product Users may refer to the product page at AAEON com for the latest version of this document ...

Page 6: ...transient over voltage 7 Always disconnect this device from any AC supply before cleaning 8 While cleaning use a damp cloth instead of liquid or spray detergents 9 Make sure the device is installed near a power outlet and is easily accessible 10 Keep this device away from humidity 11 Place the device on a solid surface during installation to prevent falls 12 Do not cover the openings on the device...

Page 7: ...usion to the device iii Exposure to moisture iv Device is not working as expected or in a manner as described in this manual v The device is dropped or damaged vi Any obvious signs of damage displayed on the device 18 DO NOT LEAVE THIS DEVICE IN AN UNCONTROLLED ENVIRONMENT WITH TEMPERATURES BEYOND THE DEVICE S PERMITTED STORAGE TEMPERATURES SEE CHAPTER 1 TO PREVENT DAMAGE ...

Page 8: ...plosion if the battery is incorrectly replaced Replace only with the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufacturer s instructions and your local government s recycling or disposal directives Attention Il y a un risque d explosion si la batterie est remplacée de façon incorrecte Ne la remplacer qu avec le même modèle ou équivalent re...

Page 9: ...名称及含量 AAEON Main Board Daughter Board Backplane 部件名称有毒有害物质或元素铅 Pb 汞 Hg 镉 Cd 六价铬 Cr VI 多溴联苯 PBB 多溴二苯醚 PBDE 印刷电路板及其电子组件 X X 外部信号连接器及线材 X X O 表示该有毒有害物质在该部件所有均质材料中的含量均在 SJ T 11363 2006 标准规定的限量要求以下 X 表示该有毒有害物质至少在该部件的某一均质材料中的含量超出 SJ T 11363 2006 标准规定的限量要求备注此产品所标示之环保使用期限系指在一般正常使用状况下 ...

Page 10: ...henyl Ethers PBDE PCB Other Components X X O O O Wires Connectors for External Connections X X O O O O O The quantity of poisonous or hazardous substances or elements found in each of the component s parts is below the SJ T 11363 2006 stipulated requirement X The quantity of poisonous or hazardous substances or elements found in at least one of the component s parts is beyond the SJ T 11363 2006 s...

Page 11: ... LVDS eDP Power Selection JP3 10 2 3 4 Auto Power Button Enable Disable JP4 11 2 3 5 COM 1 Pin 8 Function Selection JP5 11 2 4 List of Connectors 12 2 4 1 RTC Battery Connector CN1 14 2 4 2 Audio Connector CN2 14 2 4 3 M 2 2280 M Key CN3 15 2 4 4 M 2 2230 E Key CN4 18 2 4 5 Mini Card CN5 21 2 4 6 LVDS eDP Backlight CN6 24 2 4 7 LVDS eDP Connector CN7 24 2 4 8 HDMI CN8 28 2 4 9 Display Port CN9 29 ...

Page 12: ...P Input Reserved CN27 42 2 4 25 Front Panel CN28 43 2 4 26 5VB Standby Input CN29 44 2 5 Thermal Solution 45 Chapter 3 AMI BIOS Setup 46 3 1 System Test and Initialization 47 3 2 AMI BIOS Setup 48 3 3 Setup Submenu Main 49 3 4 Setup Submenu Advanced 50 3 4 1 CPU Configuration 51 3 4 2 PCH FW Configuration 52 3 4 2 1 Firmware Update Configuration 53 3 4 3 Trusted Computing 54 3 4 4 SATA Configurati...

Page 13: ... 5 1 2 LVDS Panel Configuration 82 3 5 2 PCI Express Configuration 84 3 5 2 1 Pcie Slot M 2 KEY E 2230 CN4 85 3 5 2 2 Pcie Slot M 2 KEY E 2280 CN3 86 3 6 Setup Submenu Security 87 3 6 1 Secure Boot 88 3 6 1 1 Key Management 89 3 7 Setup Submenu Boot 91 3 7 1 BBS Priorities 92 3 8 Setup Submenu Save Exit 93 Chapter 4 Driver Installation 94 4 1 Driver Download Installation 95 Appendix A I O Informat...

Page 14: ...3 5 Subcompact Board GENE EHL7 Chapter 1 Chapter 1 Product Specifications ...

Page 15: ...or J6412 4C 4T 2 00 GHz 10W Intel Celeron Processor N6210 2C 2T 1 20 GHz 6 5W Chipset Integrated with Intel SoC Memory Type DDR4 up to 3200 Single Channel SODIMM x 1 Max 32GB Non ECC IBECC supported by selected CPU SKU BIOS UEFI Wake on LAN Yes Watchdog Timer 255 Levels Security TPM 2 0 Optional RTC Battery Lithium Battery 3V 240mAh Dimension 5 75 x 4 146mm x 101 6mm Weight 0 83 lb 0 38Kg OS Suppo...

Page 16: ...ax Display Controller Intel UHD Graphics for 10th Gen Intel Processors LVDS eDP LVDS x 1 Dual Channel 18 24 bit up to 1920 x 1080 Display Interface HDMI 1 4 x 1 up to 3840 x 2160 30Hz DP 1 4 x 1 up to 3840 x 2160 120Hz Multiple Display Up to 3 Simultaneous Displays Audio Codec Realtek ALC897 Audio Interface Line In Line Out Mic Speaker External I O Ethernet Realtek RTL8111H CG 1GbE RJ 45 x 2 USB U...

Page 17: ...1 DIO GPIO GPIO 8 bits SMBus I2C SMBus I2C x 1 Default SMBus Touch Fan 4 pin Smart Fan x 1 SIM Front Panel HDD LED PWR LED Power Button Buzzer Reset Expansion Mini PCIe mSATA Full size mPCIe x 1 M 2 M 2 2230 E Key x 1 PCIe 3 0 x1 USB 2 0 M 2 2280 M Key x 1 PCIe 3 0 x2 SATA SATA select by BOM Environment Operating Temperature 32 F 140 F 0 C 60 C Storage Temperature 40 F 185 F 40 C 85 C Operating Hu...

Page 18: ...Chapter 1 Product Specifications 5 3 5 Subcompact Board GENE EHL7 1 2 Block Diagram ...

Page 19: ...3 5 Subcompact Board GENE EHL7 Chapter 2 Chapter 2 Hardware Information ...

Page 20: ...Chapter 2 Hardware Information 7 3 5 Subcompact Board GENE EHL7 2 1 Dimensions ...

Page 21: ...Chapter 2 Hardware Information 8 3 5 Subcompact Board GENE EHL7 2 2 Jumpers and Connectors ...

Page 22: ...l of the board s jumpers that you can configure for your application Label Function JP1 Clear CMOS Jumper JP2 LVDS eDP BKLT Power Selection JP3 LVDS eDP Power Selection JP4 Auto Power Button Enable Disable JP5 COM 1 Pin 8 Function Selection 2 3 1 Clear CMOS Jumper JP1 Clear CMOS Jumper 1 2 Save CMOS Default 2 3 Clear CMOS ...

Page 23: ...nformation 10 3 5 Subcompact Board GENE EHL7 2 3 2 LVDS eDP BKLT Power Selection JP2 LVDS eDP BKLT Power Selection 1 2 12V 2 3 5V Default 2 3 3 LVDS eDP Power Selection JP3 LVDS eDP Power Selection 1 2 5V 2 3 3 3V Default ...

Page 24: ... Subcompact Board GENE EHL7 2 3 4 Auto Power Button Enable Disable JP4 Auto Power Button Enable Disable 1 2 Disable 2 3 Enable Default 2 3 5 COM 1 Pin 8 Function Selection JP5 COM 1 Pin 8 Function Selection 1 2 12V 3 4 Ring Default 5 6 5V ...

Page 25: ... Connector CN2 Audio Connector CN3 M 2 2280 M Key CN4 M 2 2230 E Key CN5 Mini Card CN6 LVDS eDP Backlight CN7 LVDS eDP Connector CN8 HDMI CN9 Display Port CN10 RJ 45 CN11 RJ 45 CN12 SATA CN13 SATA power CN14 GPIO Connector CN15 Dual USB 3 0 Type A Connector CN16 19 Internal USB 2 0 Connector CN20 COM Port RS 232 422 485 CN21 COM Port RS 232 CN22 SPI For BIOS CN23 I2C SMBus CN24 Debug Port ESPI CN2...

Page 26: ...Chapter 2 Hardware Information 13 3 5 Subcompact Board GENE EHL7 Label Function CN27 12V Input 4P Colay CN28 Front Panel CN29 5VB Standby Input CN30 12V Input New Colay ...

Page 27: ...C Battery Connector CN1 Pin Pin Name Signal Type Signal Level 1 3 3V PWR 3 3V 2 GND GND 2 4 2 Audio Connector CN2 Pin Pin Name Signal Type Signal Level 1 LOUT_R Signal 2 MIC_R Signal 3 LOUT_L Signal 4 MIC_L Signal 5 JD_LOUT Signal 6 JD_MIC Signal 7 AUD_GND GND 8 AUD_GND GND ...

Page 28: ...Signal Level 9 JD_LIN Signal 10 LIN_R Signal 11 V5A_AUD PWR 5V 12 LIN_L Signal 13 AUD_GND GND 14 AUD_GND GND 2 4 3 M 2 2280 M Key CN3 Pin Pin Name Signal Type Signal Level 1 GND GND 2 V3P3A PWR 3 3V 3 GND GND 4 V3P3A PWR 3 3V 5 PCIE_3_RXN DIFF 6 CARD_PWR_OFF 7 PCIE_3_RXP DIFF 8 NC 9 GND GND ...

Page 29: ...IE_3_TXN DIFF 12 V3P3A PWR 3 3V 13 PCIE_3_TXP DIFF 14 V3P3A PWR 3 3V 15 GND GND 16 V3P3A PWR 3 3V 17 PCIE_2_RXN DIFF 18 V3P3A PWR 3 3V 19 PCIE_2_RXP DIFF 20 NC 21 GND GND 22 NC 23 PCIE_2_TXN DIFF 24 NC 25 PCIE_2_TXP DIFF 26 NC 27 GND GND 28 NC 29 PCIE_1_RXN DIFF 30 NC 31 GND GND 32 NC 33 GND GND 34 NC 35 PCIE_1_TXN DIFF ...

Page 30: ...evel 36 NC 37 PCIE_1_TXP DIFF 38 DEVSLP 39 GND GND 40 SMCLK 41 PCIE_0_RXN DIFF 42 SMDAT 43 PCIE_0_RXP DIFF 44 NC 45 GND GND 46 NC 47 PCIE_0_TXN DIFF 48 NC 49 PCIE_0_TXP DIFF 50 PERST 51 GND GND 52 CLKREQ 53 NC 54 PEWARK 55 PCIE_0_CLK_DN DIFF 56 NC 57 PCIE_0_CLK_DP DIFF 58 NC 67 NC 68 SSCLK 69 PEDET ...

Page 31: ...ame Signal Type Signal Level 70 V3P3A PWR 3 3V 71 GND GND 72 V3P3A PWR 3 3V 73 GND GND 74 V3P3A PWR 3 3V 75 GND GND 2 4 4 M 2 2230 E Key CN4 Pin Pin Name Signal Type Signal Level 1 GND GND 2 V3P3A PWR 3 3V 3 USB_D DIFF 4 V3P3A PWR 3 3V 5 USB_D DIFF 6 LED1 7 GND GND 8 NC 9 NC ...

Page 32: ... Pin Pin Name Signal Type Signal Level 10 NC 11 NC 12 NC 13 GND GND 14 NC 15 NC 16 NC 17 NC 18 GND GND 19 NC 20 NC 21 NC 22 NC 23 NC 32 NC 33 GND GND 34 NC 35 PCIE_5_TXP DIFF 36 NC 37 PCIE_5_TXN DIFF 38 NC 39 GND GND 40 NC 41 PCIE_4_RXP DIFF 42 NC 43 PCIE_4_RXN DIFF ...

Page 33: ...gnal Type Signal Level 44 NC 45 GND GND 46 NC 47 PCIE_1_CLK_DP DIFF 48 NC 49 PCIE_1_CLK_DN DIFF 50 SUSCLK 51 GND GND 52 PERST0 53 PCIE_CLKREQ 54 W_DISABLE2 55 PCIE_WAKE 56 W_DISABLE1 57 GND GND 58 NC 59 I2C_DATA 60 I2C_CLK 61 NC 62 NC 63 NC 64 NC 65 NC 66 NC 67 NC 68 NC 69 GND GND ...

Page 34: ...e Signal Type Signal Level 70 V3P3A_2242 PWR 3 3V 71 NC 72 V3P3A_2242 PWR 3 3V 73 NC 74 V3P3A_2242 PWR 3 3V 75 GND GND 2 4 5 Mini Card CN5 Pin Pin Name Signal Type Signal Level 1 PCIE_WAKE IN 2 3 3VSB PWR 3 3V 3 NC 4 GND GND 5 NC 6 1 5V PWR 1 5V 7 PCIE_CLK_REQ IN 8 UIM_PWR PWR ...

Page 35: ... DIFF 12 UIM_CLK IN 13 PCIE_REF_CLK DIFF 14 UIM_RST IN 15 GND GND 16 UIM_VPP PWR 17 NC 18 GND GND 19 NC 20 W_DISABLE OUT 3 3V 21 GND GND 22 BUF_PLT_RST OUT 3 3V 23 PCIE_RX DIFF 24 3 3VSB PWR 3 3V 25 PCIE_RX DIFF 26 GND GND 27 GND GND 28 1 5V PWR 1 5V 29 GND GND 30 SMB_CLK I O 3 3V 31 PCIE_TX DIFF 32 SMB_DATA I O 3 3V 33 PCIE_TX DIFF 34 GND GND ...

Page 36: ...oard GENE EHL7 Pin Pin Name Signal Type Signal Level 35 GND GND 36 USB_D DIFF 37 GND GND 38 USB_D DIFF 39 3 3VSB PWR 3 3V 40 GND GND 41 3 3VSB PWR 3 3V 42 NC 43 GND GND 44 NC 45 NC 46 NC 47 NC 48 1 5V PWR 1 5V 49 NC 50 GND GND 51 NC 52 3 3VSB PWR 3 3V ...

Page 37: ... Pin Name Signal Type Signal Level 1 BKL_PWR PWR 5V 12V 2 BKL_PWR PWR 5V 12V 3 BKL_CONTROL OUT 4 GND GND 5 GND GND 6 BKL_ENABLE OUT 5V Note LVDS BKL_PWR can be set to 5V or 12V by JP2 2 4 7 LVDS eDP Connector CN7 LVDS Function Pin Pin Name Signal Type Signal Level 1 BKL_ENABLE OUT 2 BKL_CONTROL OUT ...

Page 38: ...6 PWR PWR 3 3V 5V 7 LVDSA_CLK DIFF 8 PWR PWR 3 3V 5V 9 GND GND 10 GND GND 11 LVDSA_DATA0 DIFF 12 LVDSA_DATA2 DIFF 13 LVDSA_DATA0 DIFF 14 LVDSA_DATA2 DIFF 15 GND GND 16 GND GND 17 LVDSA_DATA1 DIFF 18 LVDSA_DATA3 DIFF 19 LVDSA_DATA1 DIFF 20 LVDSA_DATA3 DIFF 21 GND GND 22 GND GND 23 LVDSB_D0 DIFF 24 LVDS_DDC_DATA 25 LVDSB_D0 DIFF 26 LVDS_DDC_CLK 27 GND GND ...

Page 39: ...2 DIFF 31 LVDSB_DATA1 DIFF 32 LVDSB_DATA2 DIFF 33 GND GND 34 GND GND 35 LVDSB_CLK DIFF 36 LVDSB_DATA3 DIFF 37 LVDSB_CLK DIFF 38 LVDSB_DATA3 DIFF 39 EDP _LVDS_ HPD 40 NC eDP Function Pin Pin Name Signal Type Signal Level 1 BKL_ENABLE OUT 2 BKL_CONTROL OUT 3 GND GND 4 GND GND 5 DDI0_LANE3_DN DIFF 6 PWR PWR 3 3V 5V 7 DDI0_LANE3_DP DIFF 8 PWR PWR 3 3V 5V 9 GND GND ...

Page 40: ... Signal Level 10 GND GND 11 DDI0_LANE2_DN DIFF 12 DDI0_LANE0_DN DIFF 13 DDI0_LANE2_DP DIFF 14 DDI0_LANE0_DP DIFF 15 GND GND 16 GND GND 17 DDI0_LANE1_DN DIFF 18 NC 19 DDI0_LANE1_DP DIFF 20 NC 21 GND GND 22 GND GND 23 NC 24 NC 25 NC 26 NC 27 GND GND 28 GND GND 29 NC 30 NC 31 NC 32 NC 33 GND GND 34 GND GND ...

Page 41: ... Type Signal Level 35 NC 36 NC 37 NC 38 NC 39 EDP _LVDS_ HPD 40 NC Note LVDS eDP LCD_PWR can be set to 3 3V or 5V by JP3 2 4 8 HDMI CN8 Pin Pin Name Signal Type Signal Level 1 HDMI_TX2 DIFF 2 GND GND 3 HDMI_TX2 DIFF 4 HDMI_TX1 DIFF 5 GND GND 6 HDMI_TX1 DIFF 7 HDMI_TX0 DIFF 8 GND GND 9 HDMI_TX0 DIFF ...

Page 42: ... Level 10 HDMI_CLK DIFF 11 GND GND 12 HDMI_CLK DIFF 13 NC 14 NC 15 DDC_CLK Signal 5V 16 DDC_DATA Signal 5V 17 GND GND 18 5V PWR 5V 19 HDMI_HPD 2 4 9 Display Port CN9 Pin Pin Name Signal Type Signal Level 1 DP_D0_P DIFF 2 GND GND 3 DP_D0_N DIFF 4 DP_D1_P DIFF 5 GND GND 6 DP_D1_N DIFF 7 DP_D2_P DIFF ...

Page 43: ... 9 DP_D2_N DIFF 10 DP_D3_P DIFF 11 GND GND 12 DP_D3_N DIFF 13 GND GND 14 GND GND 15 DP_AUX_P Signal 16 GND GND 17 DP_AUX_N Signal 18 HPD Signal 19 RTN_PWR GND 20 PWR PWR 3 3V 2 4 10 RJ 45 CN10 Pin Pin Name Signal Type Signal Level P1 LAN1_MDI0 DIFF P2 LAN1_MDI0 DIFF P3 LAN1_MDI1 DIFF P4 LAN1_MDI1 DIFF P5 LAN1_CT ...

Page 44: ...DI2 DIFF P9 LAN1_MDI3 DIFF P10 LAN1_MDI3 DIFF 11 LAN1_LED_LNK _ACT Signal 12 V3P3A VDD 3 3V 13 LAN1_LED_100 Signal 14 LAN1_LED_1000 Signal 2 4 11 RJ 45 CN11 Pin Pin Name Signal Type Signal Level P1 LAN2_MDI0 DIFF P2 LAN2_MDI0 DIFF P3 LAN2_MDI1 DIFF P4 LAN2_MDI1 DIFF P5 LAN2_CT P6 LAN2_CT P7 LAN2_MDI2 DIFF P8 LAN2_MDI2 DIFF P9 LAN2_MDI3 DIFF ...

Page 45: ...pe Signal Level P10 LAN2_MDI3 DIFF P11 LAN2_LED_LNK _ACT Signal P12 V3P3A VDD 3 3V P13 LAN2_LED_100 Signal P14 LAN2_LED_1000 Signal 2 4 12 SATA CN12 Pin Pin Name Signal Type Signal Level 1 GND GND 2 SATA_1_TXP DIFF 3 SATA_1_TXN DIFF 4 GND GND 5 SATA_1_RXN DIFF 6 SATA_1_RXP DIFF 7 GND GND ...

Page 46: ...L7 2 4 13 SATA Power CN13 Pin Pin Name Signal Type Signal Level 1 V5S VDD 5V 2 GND GND Note SATA power current max 1 5A 2 4 14 GPIO Connector CN14 Pin Pin Name Signal Type Signal Level 1 GPIO_0 Signal 2 GPIO_1 Signal 3 GPIO_2 Signal 4 GPIO_3 Signal 5 GPIO_4 Signal ...

Page 47: ...nal 7 GPIO_6 Signal 8 GPIO_7 Signal 9 V5S VDD 5V 10 GND GND Note GPIO power current max 0 5A 2 4 15 Dual USB 3 0 Type A Connector CN15 Pin Pin Name Signal Type Signal Level 1 V5A_USB12 PWR 5V 2 USB2_0_DN DIFF 3 USB2_0_DP DIFF 4 GND GND 5 USB3_0_RXN DIFF 6 USB3_0_RXP DIFF 7 GND GND 8 USB3_0_TXN DIFF 9 USB3_0_TXP DIFF ...

Page 48: ...N DIFF 12 USB2_1_DP DIFF 13 GND 14 USB3_1_RXN DIFF 15 USB3_1_RXP DIFF 16 GND 17 USB3_1_TXN DIFF 18 USB3_1_TXP DIFF Note USB 3 0 power current max 0 9A 2 4 16 Internal USB 2 0 Connectors CN16 CN17 CN18 CN19 Pin Pin Name Signal Type Signal Level 1 5VSB PWR 5V 2 D DIFF 3 D DIFF 4 GND GND 5 GND GND Note Each USB 2 0 power current max 0 5A ...

Page 49: ... Board GENE EHL7 2 4 17 COM Port RS 232 422 485 CN20 RS 232 Pin Pin Name Signal Type Signal Level 1 DCD IN 2 DSR IN 3 RX IN 4 RTS OUT 9V 5 TX OUT 9V 6 CTS IN 7 DTR OUT 9V 8 RI 5V 12V IN PWR 5V 12V 9 GND GND DCD DSR RX RTS TX CTS DTR RI 5V 12V GND 1 9 ...

Page 50: ...mation 37 3 5 Subcompact Board GENE EHL7 RS 485 Pin Pin Name Signal Type Signal Level 1 RS485_D I O 5V 2 NC 3 RS485_D I O 5V 4 NC 5 NC 6 NC 7 NC 8 NC 5V 12V PWR 5V 12V 9 GND GND RS485_D NC RS485_D NC NC NC NC NC 5V 12V GND 1 9 ...

Page 51: ...ype Signal Level 1 RS422_TX OUT 5V 2 NC 3 RS422_TX OUT 5V 4 NC 5 RS422_RX IN 6 NC 7 RS422_RX IN 8 NC 5V 12V PWR 5V 12V 9 GND GND Note RS 232 422 485 can be set by BIOS setting Default is RS 232 Note Pin 8 function can be set by JP5 RS422_TX NC RS422_TX NC RS422_RX NC RS422_RX NC 5V 12V GND 1 9 ...

Page 52: ...dware Information 39 3 5 Subcompact Board GENE EHL7 2 4 18 COM Port RS 232 CN21 RS 232 Pin Pin Name Signal Type Signal Level 1 DCD IN 2 DSR IN 3 RX IN 4 RTS OUT 9V 5 TX OUT 9V 6 CTS IN 7 DTR OUT 9V 8 RI IN 9 GND GND ...

Page 53: ...n Pin Name Signal Type Signal Level 1 SPI_SO Signal 2 GND GND 3 SPI_CLK Signal 4 V3P3A_SPI PWR 3 3V 5 SPI_SI Signal 6 SPI_CS Signal 7 NC 2 4 20 I2C SMBus CN23 Pin Pin Name Signal Type Signal Level 1 3 3V PWR 5V 2 SMB_CLK I2C_CLK DIFF 3 SMB_SDA I2C_DATA DIFF 4 SMB_ALERT INT_SERIRQ GND 5 GND GND ...

Page 54: ...el 1 ESPI_IO0 Signal 1 8V 2 ESPI_IO1 Signal 1 8V 3 ESPI_IO2 Signal 1 8V 4 ESPI_IO3 Signal 1 8V 5 V3 3S PWR 3 3V 6 ESPI_CS Signal 7 ESPI_RESET Signal 1 8V 8 GND GND 9 ESPI_CLK Signal 1 8V 10 V3P3A POWER 3 3V 2 4 22 Fan Connector CN25 Pin Pin Name Signal Type Signal Level 1 GND GND 2 V12S PWR 12V 3 FAN_TAC Signal 4 FAN_CTL Signal ...

Page 55: ...N power current max 1 0A 2 4 23 Power Input CN26 CN30 Pin Pin Name Signal Type Signal Level 1 V_IN PWR 12V 2 GND GND Note Colay CN30 2 4 24 ATX 2X2P Input Reserved CN27 Pin Pin Name Signal Type Signal Level 1 GND GND 2 GND GND 3 V_IN PWR 12V 4 V_IN PWR 12V Note CN27 only for 12V ...

Page 56: ...3 5 Subcompact Board GENE EHL7 2 4 25 Front Panel CN28 Pin Pin Name Signal Type Signal Level 1 GND GND 2 EXT_PWRBTN Signal 3 FP_IDELED Signal 4 V3P3S PWR 3 3V 5 FP_BUZZER Signal 6 V5S PWR 5V 7 GND 8 V3P3S PWR 3 3V 9 GND 10 HWRST Signal ...

Page 57: ...Chapter 2 Hardware Information 44 3 5 Subcompact Board GENE EHL7 2 4 26 5VB Standby Input CN29 Pin Pin Name Signal Type Signal Level 1 PS_ON Signal 2 GND GND 3 V5A_SB_IN PWR 5V ...

Page 58: ...Chapter 2 Hardware Information 45 3 5 Subcompact Board GENE EHL7 2 5 Thermal Solution Optional accessory GENE EHL7 HSK01 ...

Page 59: ...3 5 Subcompact Board GENE EHL7 Chapter 3 Chapter 3 AMI BIOS Setup ...

Page 60: ...nue the boot up sequence with non fatal errors System configuration verification These routines check the current system configuration stored in the CMOS memory and BIOS NVRAM If system configuration is not found or system configuration data error is detected system will load optimized default and re boot with this default system configuration automatically There are four situations in which you w...

Page 61: ...when the power is turned off To enter BIOS Setup press Del or ESC immediately while your computer is powering up The function for each interface can be found below Main Date and time can be set here Press Tab to switch between date elements Advanced Access hardware monitor and advanced board features options Chipset Host bridge parameters Boot Enable Disable Quiet Boot option Security The setup ad...

Page 62: ...Chapter 3 AMI BIOS Setup 49 3 5 Subcompact Board GENE EHL7 3 3 Setup Submenu Main ...

Page 63: ...Chapter 3 AMI BIOS Setup 50 3 5 Subcompact Board GENE EHL7 3 4 Setup Submenu Advanced ...

Page 64: ... N Number of cores to enable in each processor package Intel VMX Virtualization Technology Disabled Enabled Optimal Default Failsafe Default When enabled a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology Intel SpeedStep Disabled Enabled Optimal Default Failsafe Default Allows more than two frequency ranges to be supported ...

Page 65: ...Chapter 3 AMI BIOS Setup 52 3 5 Subcompact Board GENE EHL7 3 4 2 PCH FW Configuration ...

Page 66: ... 2 1 Firmware Update Configuration Options Summary Me FW Image Re Flash Enabled Disabled Optimal Default Failsafe Default Enable Disable Me FW Image Re Flash function FW Update Disabled Enabled Optimal Default Failsafe Default Enable Disable ME FW Update function ...

Page 67: ...w Security Device TCG EFI protocol and INT1A interface will not be available SHA 1 PCR Bank Disabled Optimal Default Failsafe Default Enabled Enable or Disable SHA 1 PCR Bank SHA256 PCR Bank Enabled Optimal Default Failsafe Default Disabled Enable or Disable SHA256 PCR Bank SHA384 PCR Bank Enabled Optimal Default Failsafe Default Disabled Enable or Disable SHA384 PCR Bank SM3_256 PCR Bank Enabled ...

Page 68: ... Optimal Default Failsafe Default Disabled Enable or Disable Endorsement Hierarchy TPM 2 0 UEFI Spec Version TCG_2 Optimal Default Failsafe Default TCG_1_2 Select the TCH2 Spec Version Support TCG_1_2 The Compatible mode for Win8 Win10 TCG_2 Support new TCG2 protocol and event format for Win10 or later Physical Presence Spec Version 1 3 Optimal Default Failsafe Default 1 2 Select to Tell O S to su...

Page 69: ...pact Board GENE EHL7 3 4 4 SATA Configuration Options Summary SATA Controller s Enabled Optimal Default Failsafe Default Disabled Enable Disable SATA Device Port Enabled Optimal Default Failsafe Default Disabled Enable or Disable SATA Port ...

Page 70: ...Chapter 3 AMI BIOS Setup 57 3 5 Subcompact Board GENE EHL7 3 4 5 Hardware Monitor Options Summary Smart Fan Disable Enable Optimal Default Failsafe Default Enables or Disables Smart Fan ...

Page 71: ...on Output PWM mode push pull Optimal Default Failsafe Default Fan 1 Smart Fan Control Manual Duty Mode Auto Duty Cycle Mode Optimal Default Failsafe Default Smart Fan Mode Select Temperature Source CPU PECI Temperature System Temperature Optimal Default Failsafe Default System Temperature 2 Select the monitored temperature source for this fan Temperature 1 60 Duty Cycle 1 85 ...

Page 72: ...Chapter 3 AMI BIOS Setup 59 3 5 Subcompact Board GENE EHL7 Options Summary Auto fan speed control Fan speed will follow different temperature by different duty cycle 1 100 3 4 6 SIO Configuration ...

Page 73: ...lt Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 3F8h IRQ 4 IO 2F8h IRQ 3 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts Mode RS232 Optimal Default Failsafe Default RS422 RS485 UART RS232 422 485 selection ...

Page 74: ...imal Default Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 2F8h IRQ 3 IO 3F8h IRQ 4 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts Mode RS232 Optimal Default Failsafe Default UART RS232 selection ...

Page 75: ...Serial Port Console Redirection Options Summary Console Redirection Disabled Optimal Default Failsafe Default Enabled Console Redirection Enable or Disable Console Redirection EMS Disabled Optimal Default Failsafe Default Enabled Console Redirection Enable or Disable ...

Page 76: ...OST Timer second 30 Optimal Default Failsafe Default Timer count set to Watch Dog Timer for POST WARNING Do not set to a value equal or shorter than normal POST time otherwise system may never complete POST unless clearing BIOS settings More than 2x normal POST time is suggested Sends watch dog before booting OS Disabled Optimal Default Failsafe Default Enabled Enabled Robot set Watch Dog Timer WD...

Page 77: ...hold BIOS from POST Delayed POST DXE phase Disabled Optimal Default Failsafe Default Enabled Enabled Robot holds BIOS before POST completion This allows BIOS POST to start with stable power or start after system is physically warmed up Note Robot does this after Sends watch dog before BIOS POST Delayed time second 10 Optimal Default Failsafe Default Period of time for Robot to hold BIOS from POST ...

Page 78: ...lect reset type robot should send on each boot Retry Count 3 Optimal Default Failsafe Default Fill retry counter here Robot will reset system at most counter times and then let system continue its POST At time After show logo Optimal Default Failsafe Default Before show logo Select robot action time After show logo Robot will do action after logo is displayed System devices are almost ready Before...

Page 79: ...fault Failsafe Default Fill hold time out here Robot will hold system no longer then time out value and then let system continue its POST At time After show logo Optimal Default Failsafe Default Before show logo Select robot action time After show logo Robot will do action after logo is displayed System devices are almost ready Before show logo Robot will do action before logo but some devices may...

Page 80: ...Subcompact Board GENE EHL7 3 4 9 1 Device Detecting Configuration Options Summary Interface Disabled Optimal Default Failsafe Default PCI DIO SMBUS Legacy I O Super I O MMIO Select interface robot should use to communicate with device ...

Page 81: ...ilsafe Default Fill FUNCTION number to a PCI device in hexadecimal Range 0 FF Device is Is not Optimal Default Failsafe Default Select that robot should or should not do action if condition met In condition Present Optimal Default Failsafe Default Specified register data Select the condition that robot should check for device Present device is detected According to register Robot read register acc...

Page 82: ...w Register offset 0 Optimal Default Failsafe Default Fill register offset or index for robot to read in hexadecimal Range 0 FF Bit offset 0 Optimal Default Failsafe Default Fill bit offset for register for robot to compare with bit value Bit value Low Optimal Default Failsafe Default High Fill bit value for robot to compare register bit with specified offset Byte value 0 Optimal Default Failsafe D...

Page 83: ...on met DIO pin DIO1 Optimal Default Failsafe Default DIO Fill DIO pin number 0 DIO01 DIO1 n and so on For COM express product 0 3 GPI0 3 n4 7 GPO0 3 Device is Is not Optimal Default Failsafe Default Select that robot should or should not do action if condition met In High Low level Low Optimal Default Failsafe Default High Select High Low level of the DIO pin that robot should do action ...

Page 84: ...ster data Select the condition that robot should check for device Present device is detected According to register Robot read register according to configuration Note Device will be considered Present by Robot when data read from device is not 0xFF Register data is bitwise equal to Optimal Default Failsafe Default bytewise equal to bytewise lesser than bytewise larger than Select how robot should ...

Page 85: ...gister bit with specified offset Byte value 0 Optimal Default Failsafe Default Fill a byte value for robot to compare register data with in hexadecimal Range 0 FF Options Summary Legacy I O I O Address 0 Optimal Default Failsafe Default Fill I O address device is responding to Range 0 FFFF Device is Is not Optimal Default Failsafe Default Select that robot should or should not do action if conditi...

Page 86: ... equal to Optimal Default Failsafe Default bytewise equal to bytewise lesser than bytewise larger than Select how robot should compare data read from register to a value configured below Bit offset 0 Optimal Default Failsafe Default Fill bit offset for register for robot to compare with bit value Bit value Low Optimal Default Failsafe Default High Fill bit value for robot to compare register bit w...

Page 87: ...a Select the condition that robot should check for device Present device is detected According to register Robot read register according to configuration Note Device will be considered Present by Robot when data read from device is not 0xFF Register data is bitwise equal to Optimal Default Failsafe Default bytewise equal to bytewise lesser than bytewise larger than Select how robot should compare ...

Page 88: ...r bit with specified offset Byte value 0 Optimal Default Failsafe Default Fill a byte value for robot to compare register data with in hexadecimal Range 0 FF Options Summary MMIO MMIO Address 0 Optimal Default Failsafe Default Fill Memory Mapped I O address device is responding to Range 0 FFFFFFFF Device is Is not Optimal Default Failsafe Default Select that robot should or should not do action if...

Page 89: ...ual to Optimal Default Failsafe Default bytewise equal to bytewise lesser than bytewise larger than Select how robot should compare data read from register to a value configured below Bit offset 0 Optimal Default Failsafe Default Fill bit offset for register for robot to compare with bit value Bit value Low Optimal Default Failsafe Default High Fill bit value for robot to compare register bit with...

Page 90: ...wer supply mode Restore AC Power Loss Last State Optimal Default Failsafe Default Always On Always Off Select power state when power is re applied after a power failure RTC wake system from S5 Disable Optimal Default Failsafe Default Fixed Time Fixed Time System will wake on the hr min sec specified n Dynamic Time System will wake on the current time Increase minute s ...

Page 91: ...I BIOS Setup 78 3 5 Subcompact Board GENE EHL7 3 4 11 Digital IO Port Configuration Options Summary GPIO Port Output Input Set GPIO as Input or Output Output Level High Low Set output level when GPIO pin is output ...

Page 92: ...Chapter 3 AMI BIOS Setup 79 3 5 Subcompact Board GENE EHL7 3 5 Setup Submenu Chipset ...

Page 93: ...Chapter 3 AMI BIOS Setup 80 3 5 Subcompact Board GENE EHL7 3 5 1 System Agent SA Configuration Options Summary VT d Disabled Enabled Optimal Default Failsafe Default VT d capability ...

Page 94: ...Chapter 3 AMI BIOS Setup 81 3 5 Subcompact Board GENE EHL7 3 5 1 1 Memory Configuration ...

Page 95: ...ions Summary LVDS Disabled Enabled Optimal Default Failsafe Default Enabled Disabled this panel LCD Panel Type 640x480 60Hz 800x480 60Hz 800x600 60Hz 1024x600 60Hz 1024x768 60Hz Optimal Default Failsafe Default 1280x768 60Hz 1280x800 60Hz 1280x1024 60Hz 1366x768 60Hz 1440x900 60Hz 1600x1200 60Hz ...

Page 96: ...1920x1200 60Hz Select LCD panel used by internal graphics device by selecting the appropriate setup item Color Depth 18 Bit Optimal Default Failsafe Default 24 Bit 36 Bit 48 Bit Select panel type Backlight Mode BIOS Application Window Slider Optimal Default Failsafe Default Select backlight control signal type ...

Page 97: ...Chapter 3 AMI BIOS Setup 84 3 5 Subcompact Board GENE EHL7 3 5 2 PCI Express Configuration ...

Page 98: ...2 1 Pcie Slot M 2 KEY E 2230 CN4 Options Summary Pcie Slot M 2 KEY E 2230 CN4 Disabled Enabled Optimal Default Failsafe Default Control the PCI Express Root Port Pcie Slot M 2 KEY E 2230 CN4 Auto Optimal Default Failsafe Default Gen1 Gen2 Gen3 Configure PCIe Speed ...

Page 99: ...2 2 Pcie Slot M 2 KEY E 2280 CN3 Options Summary Pcie Slot M 2 KEY E 2280 CN3 Disabled Enabled Optimal Default Failsafe Default Control the PCI Express Root Port Pcie Slot M 2 KEY E 2280 CN3 Auto Optimal Default Failsafe Default Gen1 Gen2 Gen3 Configure PCIe Speed ...

Page 100: ...hen the user enters the Setup utility A User Password does not provide access to many of the features in the Setup utility Select the password you wish to set and press Enter In the dialog box enter your password must be between 3 and 20 letters or numbers Press Enter and retype your password to confirm Press Enter again to set the password Removing the Password Select the password you want to rem...

Page 101: ...em is in User mode The mode change requires platform reset Secure Boot Mode Custom Optimal Default Failsafe Default Standard Secure Boot mode options Standard or Custom In Custom mode Secure Boot Policy variables can be configured by a physically present user without full authentication Restore Factory Keys Force System to User Mode Install factory default Secure Boot key databases Reset to Setup ...

Page 102: ...er mode The mode change requires platform reset Restore Factory Keys Force System to User Mode Install factory default Secure Boot key databases Reset to Setup Mode Delete all Secure Boot key databases from NVRAM Export Secure Boot variables Copy NVRAM content of Secure Boot variables to files in a root folder on a file system device Enroll Efi Image Allow the image to run in Secure Boot mode Enro...

Page 103: ... Delete Key Exchange Keys Details Export Update Append Delete Authorized Signatures Details Export Update Append Delete Forbidden Signatures Details Export Update Append Delete Authorized TimeStamps Update Append OsRecovery Signatures Update Append Enroll Factory Defaults or load certificates from a file 1 Public Key Certificate a EFI_SIGNATURE_LIST b EFI_CERT_X509 DER c EFI_CERT_RSA2048 bin d EFI...

Page 104: ...nu Boot Options Summary Quiet Boot Disabled Enabled Optimal Default Failsafe Default Enable or Disable Quiet Boot option UEFI PXE Support Disabled Optimal Default Failsafe Default Enabled Enable Disable UEFI Network Stack FIXED BOOT ORDER Priorities Sets the system boot order ...

Page 105: ...Chapter 3 AMI BIOS Setup 92 3 5 Subcompact Board GENE EHL7 3 7 1 BBS Priorities ...

Page 106: ... EHL7 3 8 Setup Submenu Save Exit Options Summary Save Changes and Reset Reset the system after saving the changes Discard Changes and Exit Exit system setup without saving any changes Restore Defaults Restore Load Default values for all the setup options ...

Page 107: ...3 5 Subcompact Board GENE EHL7 Chapter 4 Chapter 4 Driver Installation ...

Page 108: ...all them Install Chipset Drivers 1 Open the Intel Chipset folder 2 Run the SetupChipset exe in the folder 3 Follow the instructions 4 Drivers will be installed automatically Install Graphics Drivers 1 Open the Intel Graphics folder 2 Run the igxpin exe file in the folder 3 Follow the instructions 4 Drivers will be installed automatically Install LAN Driver 1 Open the Intel LAN folder 2 Run the PRO...

Page 109: ...instructions 3 Drivers will be installed automatically Install ME Drivers 1 Open the ME folder 2 Run the SetupME exe file in the folder 3 Follow the instructions 4 Drivers will be installed automatically Install Touch Drivers 1 Open the Touch folder 2 Run the Setup exe file in the folder 3 Follow the instructions 4 Drivers will be installed automatically Peripheral Drivers 1 Open the Ecilite PSE_H...

Page 110: ...3 5 Subcompact Board GENE EHL7 Appendix A Appendix A I O Information ...

Page 111: ...Appendix A I O Information 98 3 5 Subcompact Board GENE EHL7 A 1 I O Address Map ...

Page 112: ...Appendix A I O Information 99 3 5 Subcompact Board GENE EHL7 ...

Page 113: ...Appendix A I O Information 100 3 5 Subcompact Board GENE EHL7 A 2 Memory Address Map ...

Page 114: ...Appendix A I O Information 101 3 5 Subcompact Board GENE EHL7 ...

Page 115: ...Appendix A I O Information 102 3 5 Subcompact Board GENE EHL7 A 3 IRQ Mapping Chart ...

Page 116: ...Appendix A I O Information 103 3 5 Subcompact Board GENE EHL7 ...

Page 117: ...Appendix A I O Information 104 3 5 Subcompact Board GENE EHL7 ...

Page 118: ...3 5 Subcompact Board GENE EHL7 Appendix B Appendix B Mating Connectors and Cables ...

Page 119: ... 170X000152 CN7 LVDS SHDR WL1010H 2 2 LVDS Cable 170X000280 eDP JCTC 11002H0 0 2 20P eDP Cable 170X000409 CN12 SATA Molex 887505318 SATA Cable 1709070500 CN13 SATA Power JST PHR 2 SATA Power Cable 1702150155 CN14 8 bit GPIO Header TE E001H 2X5 N A N A CN16 CN19 USB2 0 Internal Molex 51021 0500 USB2 0 Cable 1700050207 CN24 eSPI Debug card JST SHR 10V S B eSPI Cable 1703100133 CN28 Front Panel Molex...

Search results

Summary of Contents for GENE-EHL7

Reviews:

Related manuals for GENE-EHL7

Brands by name

Popular brands

Aaeon GENE-EHL7, User Manual

Search results

Summary of Contents for GENE-EHL7

Reviews:

Related manuals for GENE-EHL7

Brands by name

Popular brands