Picaso Processor
Datasheet
©
2017 4D Labs Semiconductors
Page 8 of 27
www.4dsystems.com.au
Picaso Processor Pin Out (continued…)
PIN
SYMBOL
I/O
DESCRIPTION
51
BUS1
I/O
General Purpose Parallel I/O BUS(0..7), bit 1. This pin is 5.0V tolerant.
52
BUS2
I/O
General Purpose Parallel I/O BUS(0..7), bit 2. This pin is 5.0V tolerant.
53
BUS3
I/O
General Purpose Parallel I/O BUS(0..7), bit 3. This pin is 5.0V tolerant.
54
BUS4
I/O
General Purpose Parallel I/O BUS(0..7), bit 4. This pin is 5.0V tolerant.
55
BUS5
I/O
General Purpose Parallel I/O BUS(0..7), bit 5. This pin is 5.0V tolerant.
56
REF
P
Internal voltage regulator filter capacitor. Connect a 4.7uF to 10uF capacitor
from this pin to Ground.
58
WR
O
Display Write strobe signal. Picaso asserts this signal LOW when writing data to
the display. Connect this pin to the Write (WR) signal of the display.
59
RD
Display Read strobe signal. Picaso asserts this signal LOW when reading data
from the display. Connect this pin to the Read (RD) signal of the display.
60
CS
O
Display Chip Select. Picaso asserts this signal LOW when accessing the display.
Connect this pin to the Chip Select (CS) signal of the display.
61
RS
O
Display Register Select.
LOW: Display index or status register is selected.
HIGH: Display GRAM or register data is selected.
Connect this pin to the Register Select (RS or A0 or C/D or similar naming
convention) signal of the display.
62
IO4/BUS_RD
I/O
General Purpose IO4 pin. Also used for BUS_RD signal to read and latch the
data in to the parallel GPIO BUS(0..7).
63
IO3
I/O
General Purpose IO3 pin. This pin is 5.0V tolerant.
64
IO2
I/O
General Purpose IO2 pin. This pin is 5.0V tolerant.
I = Input, O = Output, P = Power, A = Analogue