Hardware Development Guide of Module Product
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4.2
Power-on/Power-off Flow
To guarantee the user can power on and power off stably, you can refer to the
power-on sequence chart as shown in Figure 4-1 and the power-off sequence chart
as shown in Figure 4-2. Table 4-3 shows the power-on and resetting time, which
needs to be paid attention to during the module power-on process.
1. Once VPH_PWR is powered on, the POWER_ON signal will be synchronized
and be established as the high PWL.
2. After VPH_PWR is established normally, the interval between it to the
POWER_ON signal cannot be too short. Refer to T2 parameter. ZTEWelink
recommends that VPH_PWR adopt the power-off plan that does not
disconnect the power supply.
3. The power-on startup time takes the lower level of POWER_ON as the starting
point, and POWER_ON needs to be released after being kept on the low PWL
for a period.
4. SUB_VBUS is the USB PHY power supply. It is not recommended to be
established before VPH_PWR.
During the process of establishing the module PINs, pay attention to the following
items:
1. To power off by the POWER_ON signal, the T4 period needs to be designed
as required.
2. After VPH_PWR and USB_VBUS are powered off, it is recommended not to
disconnect the power supply.
