Hardware Development Guide of Module Product
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3.9
JTAG (Joint Test Action Group) Interface
3.9.1
Description of PINs
The JTAG interface complies with the ANSI/ICEEE Std. 1149.1-1990 standard, and
the interface is defined as shown in Table 3-9.
Table 3-9 Definition of JTAG Signal
PIN
Signal Name
I/O Type
Function
3
JTAG_RESOUT_N DI
LGA reset
72
JTAG_TRST_N
DI-PD
JTAG reset
73
JTAG_RTCK
DO
JTAG return clock
74
JTAG_TCK
DI-PU
JTAG clock input
75
JTAG_TDO
Z
JTAG test data output
76
JTAG_TDI
DI-PU
JTAG test data input
77
JTAG_TMS
DI-PU
JTAG test mode
select
78
GND
--
Grounding
3.9.2
Application of JTAG Interface
On the system board, you need to reserve the testing point or interface of the
related JTAG signal, so as to solve the un-repairable fault of LGA module due to
emergencies such as downloading interruption.
3.10
Power-on/Power-off & Reset Signal
3.10.1
Description of PINs
The power-on process of ZM5202 module is: Push the POWER_ON PIN for more
than 50ms, pull this PIN upward and then power on. Under the power-on status,
push POWER_ON PIN for more than 5s, then pull this PIN higher, and then power
off. Within the module, POWER_ON PIN is pulled via a 200 K resistance to 1.8V
power. To power on, if it does not need to be powered down, process POWER_ON
according to the figure below.
