5-2
Z380
™
U
SER
'
S
M
ANUAL
DC-8297-03
Z
ILOG
5.2.1 Carry Flag (C)
The Carry flag is set or cleared depending on the operation
being performed. For add instructions that generate a
carry and subtract instruction generating a borrow, the
Carry flag is set to 1. The Carry flag is cleared to 0 by an add
that does not generate a carry or a subtract that generates
no borrow. This saved carry facilitates software routines for
extended precision arithmetic. The multiply instructions
use the Carry flag to signal information about the precision
of the result. Also, the Decimal Adjust Accumulator (DAA)
instruction leaves the Carry flag set to 1 if a carry occurs
when adding BCD quantities.
For rotate instructions, the Carry flag is used as a link
between the least significant and most significant bits for
any register or memory location. During shift instructions,
the Carry flag contains the last value shifted out of any
register or memory location. For logical instructions the
Carry flag is cleared. The Carry flag can also be set and
complemented with explicit instructions.
5.2.2 Add/Subtract Flag (N)
The Add/Subtract flag is used for BCD arithmetic. Since
the algorithm for correcting BCD operations is different for
addition and subtraction, this flag is used to record when
an add or subtract was last executed, allowing a subse-
quent Decimal Adjust Accumulator instruction to perform
correctly. See the discussion of the DAA instruction for
further information.
5.2.3 Parity/Overflow Flag (P/V)
This flag is set to a particular state depending on the
operation being performed.
For signed arithmetic, this flag, when set to 1, indicates that
the result of an operation on two’s complement numbers
has exceeded the largest number, or less than the smallest
number, that can be represented using two’s complement
notation. This overflow condition can be determined by
examining the sign bits of the operands and the result.
The P/V flag is also used with logical operations and rotate
instructions to indicate the parity of the result. The of bits
set to 1 in a byte are counted. If the total is odd, this flag is
reset indicates odd parity (P = 0). If the total is even, this
flag is set indicates even parity (P = 1).
During block search and block transfer instructions, the P/
V flag monitors the state of the Byte Count register (BC).
When decrementing the byte counter results in a zero
value, the flag is cleared to 0; otherwise the flag is set to 1.
During Load Accumulator with I or R register instruction,
the P/V flag is loaded with the IEF2 flag. For details on this
topic,.refer to Chapter 6, “Interrupts and Traps.”
When a byte is inputted to a register from an I/O device
addressed by the C register, the flag is adjusted to indicate
the parity of the data.
5.2.4 Half-Carry Flag (H)
The Half-Carry flag (H) is set to 1 or cleared to 0 depending
on the carry and borrow status between bits 3 and 4 of an
8-bit arithmetic operation and between bits 11 and 12 of a
16-bit arithmetic operation. This flag is used by the Deci-
mal Adjust Accumulator instruction to correct the result of
an addition or subtraction operation on packed BCD data.
5.2.5 Zero Flag (Z)
The Zero flag (Z) is set to 1 if the result generated by the
execution of certain instruction is a zero.
For arithmetic and logical operations, the Zero flag is set to
1 if the result is zero. If the result is not zero, the Zero flag
is cleared to 0.
For block search instructions, the Zero flag is set to 1 if a
comparison is found between the value in the Accumulator
and the memory location pointed to by the contents of the
register pair HL.
When testing a bit in a register or memory location, the Zero
flag contains the complemented state of the tested bit (i.e.,
the Zero flag is set to 1 if the tested bit is a 0, and vice-
versa).
For block I/O instructions, if the result of decrements B is
zero, the Zero flag is set to 1; otherwise, it is cleared to 0.
Also, for byte inputs to registers from I/O devices ad-
dressed by the C register, the Zero flag is set to 1 to
indicate a zero byte input.
5.2.6 Sign Flag (S)
The Sign flag (S) stores the state of the most significant bit
of the result. When the Z380 CPU performs arithmetic
operation on signed numbers, binary two’s complement
notation is used to represent and process numeric infor-
mation. A positive number is identified by a 0 in the most
significant bit. A negative number is identified by a 1 in the
most significant bit.
When inputting a byte from an I/O device addressed by the
C register to a CPU register, the Sign flag indicates either
positive (S = 0) or negative (S = 1) data.
