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U

SER

'

S

M

ANUAL

Z

ILOG

Source Code

Mode

Object Code

RRC

H

CB 0C

RRC

L

CB 0D

RRCA

0F

RRCW (HL)

ED CB 0A

RRCW (IX+12H)

I

DD CB 12 0A

RRCW (IY+12H)

I

FD CB 12 0A

RRCW BC

ED CB 08

RRCW DE

ED CB 09

RRCW HL

ED CB 0B

RRCW IX

ED CB 0C

RRCW IY

ED CB 0D

RRD

ED 67

RRW

(HL)

ED CB 1A

RRW

(IX+12H)

I

DD CB 12 1A

RRW

(IY+12H)

I

FD CB 12 1A

RRW

BC

ED CB 18

RRW

DE

ED CB 19

RRW

HL

ED CB 1B

RRW

IX

ED CB 1C

RRW

IY

ED CB 1D

RST

00H

X

C7

RST

08H

X

CF

RST

10H

X

D7

RST

18H

X

DF

RST

20H

X

E7

RST

28H

X

EF

RST

30H

X

F7

RST

38H

X

FF

SBC

A,(HL)

9E

SBC

A,(IX+12H) I

DD 9E

12

SBC

A,(IY+12H) I

FD 9E

12

SBC

A,12H

DE 12

SBC

A,A

9F

SBC

A,B

98

SBC

A,C

99

SBC

A,D

9A

SBC

A,E

9B

SBC

A,H

9C

SBC

A,IXL

DD 9D

SBC

A,IXU

DD 9C

SBC

A,IYL

FD 9D

SBC

A,IYU

FD 9C

SBC

A,L

9D

SBC

HL,BC

ED 42

SBC

HL,DE

ED 52

SBC

HL,HL

ED 62

SBC

HL,SP

ED 72

SBCW (IX+12H)

I

DD DE 12

SBCW (IY+12H)

I

FD DE 12

SBCW 1234H

ED 9E

34 12

SBCW BC

ED 9C

SBCW DE

ED 9D

SBCW HL

ED 9F

SBCW HL,(IX+12H)

DD DE 12

Source Code

Mode

Object Code

SBCW HL,(IY+12H)

FD DE 12

SBCW HL,1234H

ED 9E

34 12

SBCW HL,BC

ED 9C

SBCW HL,DE

ED 9D

SBCW HL,HL

ED 9F

SBCW HL,IX

DD 9F

SBCW HL,IY

FD 9F

SBCW IX

DD 9F

SBCW IY

FD 9F

SCF

37

SET

0,(HL)

CB C6

SET

0,(IX+12H)

I

DD CB 12 C6

SET

0,(IY+12H)

I

FD CB 12 C6

SET

0,A

CB C7

SET

0,B

CB C0

SET

0,C

CB C1

SET

0,D

CB C2

SET

0,E

CB C3

SET

0,H

CB C4

SET

0,L

CB C5

SET

1,(HL)

CB CE

SET

1,(IX+12H)

I

DD CB 12 CE

SET

1,(IY+12H)

I

FD CB 12 CE

SET

1,A

CB CF

SET

1,B

CB C8

SET

1,C

CB C9

SET

1,D

CB CA

SET

1,E

CB CB

SET

1,H

CB CC

SET

1,L

CB CD

SET

2,(HL)

CB D6

SET

2,(IX+12H)

I

DD CB 12 D6

SET

2,(IY+12H)

I

FD CB 12 D6

SET

2,A

CB D7

SET

2,B

CB D0

SET

2,C

CB D1

SET

2,D

CB D2

SET

2,E

CB D3

SET

2,H

CB D4

SET

2,L

CB D5

SET

3,(HL)

CB DE

SET

3,(IX+12H)

I

DD CB 12 DE

SET

3,(IY+12H)

I

FD CB 12 DE

SET

3,A

CB DF

SET

3,B

CB D8

SET

3,C

CB D9

SET

3,D

CB DA

SET

3,E

CB DB

SET

3,H

CB DC

SET

3,L

CB DD

SET

4,(HL)

CB E6

SET

4,(IX+12H)

I

DD CB 12 E6

SET

4,(IY+12H)

I

FD CB 12 E6

SET

4,A

CB E7

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Содержание Z80380

Страница 1: ...the Z380 CPU can handle Also this chapter includes a brief description of the on chip regis ters 3 Native Extended Mode Word Long Word Mode of Operation and Decoder Directives This chapter provides a...

Страница 2: ...systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the...

Страница 3: ...inter Relative loads and stores 16 bit and 24 bit Indexed offsets and in creased Indirect register addressing flexibility with all of the addressing modes allowing access to the entire 32 bit address...

Страница 4: ...297 03 ZILOG 1 1 INTRODUCTION Continued A F B C D E H L IXU IXL IYU IYL A F B C D E H L IXU IXL IYU IYL BCz DEz HLz IXz IYz BCz DEz HLz IXz IYz R I SPz PCz Iz SP PC 4 Sets of Registers Figure 1 1 Z380...

Страница 5: ...and Extended modes the Z380 drives all 32 bits of the address onto the external address bus only the width of the manipulated addresses distinguishes Native from Extended mode The Z380 CPU implements...

Страница 6: ...asic data type is the 8 bit byte which is also the basicaddressablememoryelement Thearchitecturealso supports operations on bits BCD Binary Coded Decimal digits words 16 bits or 32 bits byte strings a...

Страница 7: ...380 CPU due to the basic machine cycle s reduction to two clocks cycle from four clocks cycle on the Z80 CPU fine tuned four staged pipeline with prefetch cue This well designed pipeline and prefetch...

Страница 8: ...emory addressing space and efficient handling of nested interrupts The benefits of this architecture including high throughput rates code den sity and compiler efficiency greatly enhance the power and...

Страница 9: ...he pro gram has immediate access to both primary and alternate registers in the selected register set Changing register sets is a simple matter of an LDCTL instruction to program the Select Register S...

Страница 10: ...3 ZILOG 2 2 CPU REGISTER SPACE Continued A F B C D E H L IXU IXL IYU IYL A F B C D E H L IXU IXL IYU IYL BCz DEz HLz IXz IYz BCz DEz HLz IXz IYz R I SPz PCz Iz SP PC 4 Sets of Registers Figure 2 1 Reg...

Страница 11: ...g mode Only one register of each can be active at any given time although data in the inactive file can still be accessed by using EX IX IX and EX IY IY either in 16 bit or 32 bit wide depending on th...

Страница 12: ...of 4 Gbytes numbered consecutively in ascending order The8 bitbyteisthebasicaddressableelementintheZ380 MPU memory address space However there are other addressabledataelements bits 2 bytewords bytest...

Страница 13: ...te Address n Address n 1 32 bit word at address n D7 0 Least Significant Byte D15 8 Address n Address n 1 Address n 2 Address n 3 D31 24 Most Significant Byte D23 16 Memory addresses Least Significant...

Страница 14: ...al on chip registers which occupy an on chip I O address space This on chip I Oaddressspacecanbeaccessedonlywiththefollowing reserved on chip I O instructions which are identical to the Z180 original...

Страница 15: ...6 Internet http www zilog com 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of...

Страница 16: ...he pro gram has immediate access to both primary and alternate registers in the selected register set Changing register sets is a simple matter of an LDCTL instruction to program the Select Register S...

Страница 17: ...3 ZILOG 2 2 CPU REGISTER SPACE Continued A F B C D E H L IXU IXL IYU IYL A F B C D E H L IXU IXL IYU IYL BCz DEz HLz IXz IYz BCz DEz HLz IXz IYz R I SPz PCz Iz SP PC 4 Sets of Registers Figure 2 1 Reg...

Страница 18: ...g mode Only one register of each can be active at any given time although data in the inactive file can still be accessed by using EX IX IX and EX IY IY either in 16 bit or 32 bit wide depending on th...

Страница 19: ...of 4 Gbytes numbered consecutively in ascending order The8 bitbyteisthebasicaddressableelementintheZ380 MPU memory address space However there are other addressabledataelements bits 2 bytewords bytest...

Страница 20: ...te Address n Address n 1 32 bit word at address n D7 0 Least Significant Byte D15 8 Address n Address n 1 Address n 2 Address n 3 D31 24 Most Significant Byte D23 16 Memory addresses Least Significant...

Страница 21: ...al on chip registers which occupy an on chip I O address space This on chip I Oaddressspacecanbeaccessedonlywiththefollowing reserved on chip I O instructions which are identical to the Z180 original...

Страница 22: ...6 Internet http www zilog com 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of...

Страница 23: ...is condition it behaves exactly the same as the Z80 CPU even though it has access to the entire 4 Gbytes of memory for data access and 4G locations of I O space access to the newly added registers whi...

Страница 24: ...cution in Word mode This is useful while the Long Word LW bit in the Select Register SR is set but 16 bit data manipulation is required for this instruction The LW decoder directive causes the instruc...

Страница 25: ...00H is appended as the Most significant byte as HL31 HL24 DDIR LW LD HL 1234H Loads 00001234H into HL31 HL0 0000H is appended as the HL31 HL16 portion Zilog s products are not authorized for use as c...

Страница 26: ...e is used the instruction pro cesses data taken from one of the 8 bit registers A B C D E H L IXU IXL IYU IYL one of the 16 bit registers BC DE HL IX IY SP or one of the special byte registers I or R...

Страница 27: ...mode is located in either the I O address space I O instruction or memory address space all other instruc tions Indirect Register mode can save space and reduce ex ecution time when consecutive locati...

Страница 28: ...24 or 32 bits Operand width is affected by LW bit status for the load and exchange instructions Example of DA mode 1 Load BC register from memory location 00005E22H in Word mode LD BC 5E22H Load BC w...

Страница 29: ...offset DDIR IW for 24 bit offset Note that computation of the effective address is affected by the operation mode Native or Extended In Native mode address computation is done in modulo 216 and in Ex...

Страница 30: ...ssing allows reference forward or backward from the current Program Counter value it is used for program control instructions such as Jumps and Calls that access constants in the memory As a displacem...

Страница 31: ...culation Since this is a 4 byte instruction the PC value after fetch but before jump taking place is 19590807 00000004 1959080B The displacement portion 5000H is sign extended to a 32 bit value before...

Страница 32: ...n is done in modulo 216 mean ingcomputationisdonein16 bitanddoesnotaffectupper halfoftheSPportionforcalculation wraparoundwithinthe 16 bit In Extended mode address computation is done in modulo 232 Al...

Страница 33: ...sign extended to a 32 bit value before the address calculation and calculation is done in modulo 232 07FF7F00 FFFFFFFC 07FF7EFC 3 Load HL from location SP 10000H in Extended mode Long Word mode SETC X...

Страница 34: ...move instructions allow strings of bytes words in memory to be moved from one location to another Block search instruc tionsprovideforscanningstringsofbytes wordsinmemory to locate a particular value...

Страница 35: ...ed instructions in that the result of executing one instruction may alter the flags and the resulting value of the flags can be used to determine the operation of a subse quent instruction The program...

Страница 36: ...arity P 1 During block search and block transfer instructions the P V flag monitors the state of the Byte Count register BC When decrementing the byte counter results in a zero value the flag is clear...

Страница 37: ...itself Table 5 1 lists the condition code mnemonic the flag setting it represents and the binary encoding for each condition code Table 5 1 Condition codes Condition Codes for Jump Call and Return In...

Страница 38: ...ars this bit selecting IY 5 3 3 IX Bank Select IXBANK This 2 bit field selects the register set to be used for the IX and IX registers This field can be set independently of the register set selection...

Страница 39: ...Resetisanasynchronouseventgeneratedby outside circuits It terminates all current activities and puts the CPU into a known state Interrupts and Traps are discussed in detail in Chapter 6 and Reset is...

Страница 40: ...le5 2 includesloadinstruc tions for transferring data between byte registers transfer ring data between a byte register and memory and load ing immediate data into byte register or memory For the supp...

Страница 41: ...upported sources are listed in Table 5 7 Swap instructions allows swapping of the contents of the Word wide register BC DE HL IX or IY with its Extended portion These instructions are useful to manipu...

Страница 42: ...ptible this is essential since the repetition count can be as high as 65536 The instruction can be interrupted after any interaction in which case the address of the instruction itself rather than nex...

Страница 43: ...ruction itself or from memory For memory addressing modes followsaresupported IndirectRegister Indexed and Direct Address except multiplies which returns the 16 bit result to the same register by mult...

Страница 44: ...SP nn src X AND Word ANDW HL src src Complement Accumulator CPLW HL dst Compare Word CPW HL src src Decrement Word DEC W dst dst X Divide Unsigned DIVUW HL src src Extend Sign Word EXTSW HL dst Incre...

Страница 45: ...D E H L HL IX d IY d Bit Test BIT dst Reset Bit RES dst Rotate Left RL dst Rotate Left Accumulator RLA Rotate Left Circular RLC dst Rotate Left Circular Accumulator RLCA Rotate Left Digit RLD Rotate...

Страница 46: ...current contents of the PC are pushed onto the stack and the effective address indicated by the instruction is loaded Table 5 13 Program Control Group Instructions Instruction Name Format nn PC d HL I...

Страница 47: ...structionsfortransferringasingleword INW OUTW can transfer data between the register pair and the periph eral port specified by the contents of the C register For Word I O the contents of B D or H app...

Страница 48: ...t Decrement and Repeat Word INDRW Input and Increment Byte INI Input and Increment Word INIW Input Increment and Repeat Byte INIR Input Increment and Repeat Word INIRW Output OUT C src src A B C D E H...

Страница 49: ...tructions for transferring blocks of data from memory to Internal I O locations The operation of these instructions is very similar to that of the block move instructions described earlier with the ex...

Страница 50: ...uses the alter nate bank to save a register for the first time and saves registers into memory thereafter Mode Test instructions reports the current mode of opera tion Native Extended Word Long Word...

Страница 51: ...d description a listing of all the flags that are affected by the instruction and illustrations of the opcodes for all variants of the instruction Symbols The following symbols are used to describe th...

Страница 52: ...the table replace d value with the real number The results being 76 543 210 HEX 11 011 101 DD 01 110 001 71 00 010 010 21 5 7 EXECUTION TIME i in the execution time column indicates an I O read opera...

Страница 53: ...N A N A N A N A 1X External I O Write 1 2 1 2 N A N A N A N A N A N A 2X External I O Read 9 11 9 11 N A N A N A N A N A N A 2X External I O Write 1 3 1 3 N A N A N A N A N A N A 4X External I O Read...

Страница 54: ...if the result is zero cleared otherwise H Set if there is a carry from bit 3 of the result cleared otherwise V Set if arithmetic overflow occurs that is if both operands cleared otherwise N Cleared C...

Страница 55: ...if the result is negative cleared otherwise Z Set if the result is zero cleared otherwise H Set if there is a carry from bit 11 of the result cleared otherwise V Set if arithmetic overflow occurs that...

Страница 56: ...o cleared otherwise H Set if there is a carry from bit 11 of the result cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opp...

Страница 57: ...ere is a carry from bit 3 of the result cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise N C...

Страница 58: ...length of the operand is controlled by the Extended Native mode selection which is consistent with the manipulation of an address by the instruction Flags S Unaffected Z Unaffected H Set if there is a...

Страница 59: ...ed in the SP register This has the effect of allocating or allocating space on the stack Two s complement addition is performed Flags S Unaffected Z Unaffected H Set if there is a carry from bit 11 of...

Страница 60: ...Set if there is a carry from bit 11 of the result cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared ot...

Страница 61: ...red The contents of the source are unaffected Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if all bits of the result are zero cleared otherwise H Set P Set if t...

Страница 62: ...a 0 is stored The contents of the source are unaffected Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if all bits of the result are zero cleared otherwise H Set...

Страница 63: ...be tested is specified by a 3 bit field in the instruction this field contains the binary encoding for the bit number to be tested The bit number b must be between 0 and 7 Flags S Unaffected Z Set if...

Страница 64: ...am to determine the state of the machine Flags S Set if the alternate bank IX is in use cleared otherwise Z Set if the alternate bank IY is in use cleared otherwise H Unaffected V Set if the alternate...

Страница 65: ...n byte following the Call instruction The destination address is then loaded into the PC and points to the first instruction of the called procedure At the end of a procedure a Return instruction RET...

Страница 66: ...e a RETurn instruction is used to return to the original program These instructions employ either an 8 bit 16 bit or 24 bit signed two s complement displacement from the PC to permit calls within the...

Страница 67: ...n C NOT C The Carry flag is inverted Flags S Unaffected Z Unaffected H The previous state of the Carry flag V Unaffected N Cleared C Set if the Carry flag was clear before the operation cleared otherw...

Страница 68: ...Set if there is a borrow from bit 4 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the operands are of different signs and the result is of the same sign as the source...

Страница 69: ...ise H Set if there is a borrow from bit 12 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the operands are of different signs and the result is of the same sign as the...

Страница 70: ...tes are unaffected Two s complement subtraction is performed Next the HL register is decremented by one thus moving the pointer to the previous element in the string The BC register used as a counter...

Страница 71: ...er is decremented by one thus moving the pointer to the previous element in the string TheBCregister usedasacounter isthendecrementedbyone Iftheresultofdecrementing the BC register is not zero and no...

Страница 72: ...rybytesareunaffected Two scomplementsubtractionisperformed Nextthe HL register is incremented by one thus moving the pointer to the next element in the string The BC register used as a counter is then...

Страница 73: ...s incremented by one thus moving the pointer to the next element in the string The BC register used as a counter is then decremented by one If the result of decrementing the BC register is not zero an...

Страница 74: ...CPL A Operation A NOT A Thecontentsoftheaccumulatorarecomplemented one scomplement all1sarechanged to 0 and vice versa Flags S Unaffected Z Unaffected H Set V Unaffected N Set C Unaffected Addressing...

Страница 75: ...tion HL 15 0 NOT HL 15 0 The contents of the HL register are complemented ones complement all 1s are changed to 0 and vice versa Flags S Unaffected Z Unaffected H Set V Unaffected N Set C Unaffected A...

Страница 76: ...peration DAA Bits 7 4 DAA Bits 3 0 to Byte DAA DAA 0 0 9 0 0 9 00 0 0 0 0 8 0 A F 06 0 1 ADD 0 0 9 1 0 3 06 0 0 ADC 0 A F 0 0 9 60 1 0 INC 0 9 F 0 A F 66 1 1 N 0 0 A F 1 0 3 66 1 0 1 0 2 0 0 9 60 1 0...

Страница 77: ...ct address and in front of any trailing opcode bytes Byte ordering within the instruction follows the usual convention least significant byte first followed by more significant bytes More significant...

Страница 78: ...zero cleared otherwise H Set if there is a borrow from bit 4 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the destination was 80H cleared otherwise N Set C Unaffecte...

Страница 79: ...plement subtraction is performed Note that the length of the operand is controlledbytheExtended Nativemodeselection whichisconsistentwiththemanipulation of an address by the instruction Flags S Unaffe...

Страница 80: ...r and then clear the Interrupt Enable Flag IEF1 in the Select Register SR if the least significant bit of the argument is set disabling maskable interrupts Bits 7 5 of the argument are ignored If no a...

Страница 81: ...ero flag is set according to the value of the quotient Case 2 If the divisor is zero the HL register is unchanged the Zero and Overflow flags are set to 1 and the Sign flag is cleared to 0 Case 3 If t...

Страница 82: ...of loop control The destination address is calculated using Relative addressing The displacement in the instruction is added to the PC the PC value used is the address of the instruction following the...

Страница 83: ...the Interrupt Enable Flag IEF1 in the Select Register SR if the least significant bit of the argument is set enabling maskable interrupts Bits 7 5 of the argument are ignored If no argument is presen...

Страница 84: ...ch controls the selection of primary or alternate bank for the accumulator and flag register is complemented thus effectively exchanging the accumulator and flag registers between the two banks Flags...

Страница 85: ...0 The contents of the destination register are exchanged with the top of the stack In Long Word mode this exchange is two words otherwise it is one word Flags S Unaffected Z Unaffected H Unaffected V...

Страница 86: ...are exchanged with the contents of the source Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R EX BC D...

Страница 87: ...hanged with the contents of the source where the destination is a register in the primary bank and the source is the corresponding register in the alternate bank Flags S Unaffected Z Unaffected H Unaf...

Страница 88: ...ntents of the source where the destination is a word register in the primary bank and the source is the corresponding word register in the alternate bank Flags S Unaffected Z Unaffected H Unaffected V...

Страница 89: ...ntents of the accumulator are exchanged with the contents of the source Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Execute Mode Syntax Instruction F...

Страница 90: ...ect Register SR which control the selection of primary or alternate bank for the BC DE HL IX and IY registers are complemented thus effectively exchanging the BC DE HL IX and IY registers between the...

Страница 91: ...r considered as a signed two s complement integer are sign extended to 16 bits and the result is stored in the HL register The contents of the accumulator are unaffected This instruction is useful for...

Страница 92: ...of the HL register considered as a signed two s complement integer are sign extended to 32 bits in the HL register This instruction is useful for conversion of 16 bit signed operands into 32 bit signe...

Страница 93: ...R which controls the selection of primary or alternate bank for the BC DE and HL registers is complemented thus effectively exchanging the BC DE and HL registers between the two banks Flags S Unaffect...

Страница 94: ...egister SR which controls the selection of primary or alternate bank for the IX register is complemented thus effectively exchanging the IX register between the two banks Flags S Unaffected Z Unaffect...

Страница 95: ...egister SR which controls the selection of primary or alternate bank for the IY register is complemented thus effectively exchanging the IY register between the two banks Flags S Unaffected Z Unaffect...

Страница 96: ...r reset request is accepted After an interrupt is serviced the instruction following HALT is executed While the CPU is halted memory refresh cycles still occur and bus requests are honored When this i...

Страница 97: ...r a description of the various modes for responding to interrupts The current interrupt mode can be read from the Select Register SR Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffec...

Страница 98: ...on the contents of the 32 bit BC register are placed on the address bus Flags S Set if the input data is negative cleared otherwise Z Set if the input data is zero cleared otherwise H Cleared P Set if...

Страница 99: ...contents of the 32 bit BC register are placed on the address bus Flags S Set if the input data is negative cleared otherwise Z Set if the input data is zero cleared otherwise H Cleared P Set if the in...

Страница 100: ...ction the 8 bit peripheral address from the instruction is placed on the low byte of the address bus the contents of the accumulator are placed on address lines A15 A8 and the high order address lines...

Страница 101: ...ipheral address is placed on the low byte of the address bus and zeros are placed on all other address lines When the second opcode byte is 30h no data is stored in a destination only the flags are up...

Страница 102: ...ing the I O transaction the peripheral address from the instruction is placed on the address bus Any bytes of address not specified in the instruction are driven on the address lines as all zeros Flag...

Страница 103: ...During the I O transaction the peripheral address from the instruction is placed on the address bus Any bytes of address not specified in the instruction are driven on the address lines as all zeros F...

Страница 104: ...o cleared otherwise H Set if there is a carry from bit 3 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the destination was 7FH cleared otherwise N Cleared C Unaffected...

Страница 105: ...nt addition is performed Note that the length of the operand is controlled by the Extended Native mode selection which is consistent with the manipulation of an address by the instruction Flags S Unaf...

Страница 106: ...seable as part of a fixed port address First the byte of data from the selected peripheral is loaded into the memory location addressed by the HL register Then the B register used as a counter is decr...

Страница 107: ...a from the selected peripheral is loaded into the memory location addressed by the HL register Then the BC register used as a counter is decremented by one The HL register is then decremented by two t...

Страница 108: ...n addressed by the HL register Then the B register used as a counter is decremented by one The HL register is then decremented by one thus moving the pointer to the next destination for the input If t...

Страница 109: ...Then the BC register used as a counter is decremented by one The HL register is then decremented by two thus moving the pointer to the next destination for the input If the result of decrementing the...

Страница 110: ...seable as part of a fixed port address First the byte of data from the selected peripheral is loaded into the memory location addressed by the HL register Then the B register used as a counter is decr...

Страница 111: ...a from the selected peripheral is loaded into the memory location addressed by the HL register Then the BC register used as a counter is decremented by one The HL register is then incremented by two t...

Страница 112: ...n addressed by the HL register Then the B register used as a counter is decremented by one The HL register is then incremented by one thus moving the pointer to the next destination for the input If t...

Страница 113: ...counter is decremented by one The HL register is then incremented by two thus moving the pointer to the next destination for the input If the result of decrementing the BC register is 0 the instructio...

Страница 114: ...ss otherwise the instruction following the Jump instruction is executed Each of the Zero Carry Sign and Overflow flags can be individually tested and a jump performed conditionally on the setting of t...

Страница 115: ...address is calculated using relative addressing The displacement in the instruction is added to the PC value for the instruction following the JR instruction not the value of the PC for the JR instru...

Страница 116: ...Note R LD A R 01111 r 2 RX LD A RX 11y11101 0111110w 2 IM LD A n 00111110 n 2 IR LD A HL 01111110 2 r LD A IR 000a1010 2 r DA LD A nn 00111010 n low n high 3 r I X LD A XY d 11y11101 01111110 d 4 r I...

Страница 117: ...tion Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R LD R n 00 r 110 n 2 RX LD RX n 11y11101 0010w110...

Страница 118: ...e word of immediate data is loaded into the destination Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note...

Страница 119: ...se begin dst 15 0 nn end The word of immediate data is loaded into the destination Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Execute Mode Syntax In...

Страница 120: ...Rd RX 11y11101 01 ra10w 2 LD RXa RXb 11y11101 0110a10b 2 IM LD R n 00 r 110 n 2 IR LD R HL 01 r 110 5 w X LD R XY d 11y11101 01 r 110 d 7 w I Load from Register Addressing Execute Mode Syntax Instruct...

Страница 121: ...r Addressing Execute Mode Syntax Instruction Format Time Note R LD Rd Rs 11rs1101 00rd0010 2 L RX LD R RX 11y11101 00rr1011 2 L IR LD R IR 11011101 00rr11ri 2 r L LD RX IR 11y11101 00ri0011 2 r L DA L...

Страница 122: ...w I L LD nn R 11101101 01ra0011 n low n high 4 w I L LD nn RX 11y11101 00100010 n low n high 4 w I L X LD XY d R 11y11101 11001011 d 00rr1011 5 w I L LD IY d IX 11111101 11001011 d 00101011 5 w I L LD...

Страница 123: ...d Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Load into Stack Pointer Addressing Execute Mode Syntax Instruction Format Time Note R LD SP HL 11111001 2 L RX LD SP RX 11y11101 1111...

Страница 124: ...uring execution of either of these instructions the Overflow flag reflects the prior state of the interrupt enable Also note that the R register does not contain the refresh address and is not modifie...

Страница 125: ...umulatorareloadedintothedestination NotethattheRregisterdoes not contain the refresh address and is not modified by refresh transactions Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Una...

Страница 126: ...15 0 end The contents of the source are loaded into the destination Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Load from I Register Addressing Execute Mode Syn...

Страница 127: ...Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Load into Control Register Addressing Execute Mode Syntax Instruction Format Time Note R LDCTL SR A 11011101 11001000 4 LDCT...

Страница 128: ...dst 31 0 src 31 0 end else begin dst 15 0 src 15 0 end The contents of the Select Register SR are loaded into the HL register Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C...

Страница 129: ...the Select Register SR If Long Word mode is not in effect the upper byte of the HL register is copied into the three most significant bytes of the select register This instruction does not modify the...

Страница 130: ...nto the location addressed by the DE register Both the DE and HL registers are then decremented by one thus moving the pointers to the preceeding elements in the string The BC register used as a count...

Страница 131: ...by the DE register Both the DE and HL registers are then decremented by two or four thus moving the pointers to the preceeding words in the array The BC register used as a byte counter is then decrem...

Страница 132: ...crementing the pointers during the transfer is important if the source and destination strings overlap with the source string starting at a lower memory address Placing the pointers at the highest add...

Страница 133: ...truction is executed 65 536 words are transferred The effect of decrementing the pointers during the transfer is important if the source and destination strings overlap with the source string starting...

Страница 134: ...d into the location addressed by the DE register Both the DE and HL registers are then incremented by one thus moving the pointers to the next elements in the string The BC register used as a counter...

Страница 135: ...by the DE register Both the DE and HL registers are then incremented by two or four thus moving the pointers to the succeeding words in the array The BC register used as a byte counter is then decrem...

Страница 136: ...incrementing the pointers during the transfer is important if the source and destination strings overlap with the source string starting at a higher memory address Placing the pointers at the lowest...

Страница 137: ...struction is executed 65 536 words are transferred The effect of incrementing the pointers during the transfer is important if the source and destination strings overlap with the source string startin...

Страница 138: ...ents of the lower byte of the source register and the product is stored in the source register Both operands Both operands are treated as unsigned binary integers Flags S Unaffected Z Unaffected H Una...

Страница 139: ...to the flags This allows the program to determine the state of the machine Flags S Set if Extended mode is in effect cleared otherwise Z Set if Long word mode is in effect cleared otherwise H Unaffect...

Страница 140: ...result if the Carry flag is cleared the product can be correctly represented in 16 bits and the upper word of the HL register merely holds sign extension data Flags S Set if the result is negative cle...

Страница 141: ...egister is required to represent the result if the Carry flag is cleared the product can be correctly represented in 16 bits and the upper word of the HL register merely holds zero Flags S Cleared Z S...

Страница 142: ...erpart for this case the Overflow flag is set to 1 Flags S Set if the result is negative cleared otherwise Z Set if the result is zero cleared otherwise H Set if there is a borrow from bit 4 of the re...

Страница 143: ...e counterpart for this case the Overflow flag is set to 1 Flags S Set if the result is negative cleared otherwise Z Set if the result is zero cleared otherwise H Set if there is a borrow from bit 4 of...

Страница 144: ...DC 8297 03 ZILOG NOP NO OPERATION NOP Operation None No operation Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format...

Страница 145: ...bit is stored The contents of the source are unaffected Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if all bits of the result are zero cleared otherwise H Cle...

Страница 146: ...wise a 0 bit is stored The contents of the source are unaffected Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if all bits of the result are zero cleared otherwi...

Страница 147: ...ster The C register holding the port address is decremented by one to select the next output port The B register used as a counter is then decremented by one The HL register is then decremented by one...

Страница 148: ...the port address is decremented by one to select the next output port The B register used as a counter is then decremented by one The HL register is then decremented by one thus moving the pointer to...

Страница 149: ...d by one The byte of data from the memory location addressed by the HL register is loaded into the selected peripheral The HL register is then decremented by one thus moving the pointer to the next so...

Страница 150: ...aded into the selected peripheral The HL register is then decremented by two thus moving the pointer to the next source for the output If the result of decrementing the BC register is 0 the instructio...

Страница 151: ...C register TheCregister holdingtheportaddress isincrementedbyonetoselectthenextoutputport The B register used as a counter is then decremented by one The HL register is then incremented by one thus m...

Страница 152: ...ldingtheportaddress isincrementedbyonetoselectthenextoutputport The B register used as a counter is then decremented by one The HL register is then incremented by one thus moving the pointer to the ne...

Страница 153: ...d by one The byte of data from the memory location addressed by the HL register is loaded into the selected peripheral The HL register is then incremented by one thus moving the pointer to the next so...

Страница 154: ...aded into the selected peripheral The HL register is then incremented by two thus moving the pointer to the next source for the output If the result of decrementing the BC register is 0 the instructio...

Страница 155: ...d peripheral During the I O transaction the contents of the 32 bit BC register are placed on the address bus Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Address...

Страница 156: ...uring the I O transaction the contents of the 32 bit BC register are placed on the address bus Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Execute Mo...

Страница 157: ...saction the 8 bit peripheral address from the instruction is placed on the low byte of the address bus the contents of the accumulator are placed on address lines A 15 8 and the high order address lin...

Страница 158: ...hough the I O address will appear on the address bus and the write data will appear on the data bus while this internal write is occurring The peripheral address is placed on the low byte of the addre...

Страница 159: ...ng the I O transaction the peripheral address from the instruction is placed on the address bus Any bytes of address not specified in the instruction are driven on the address lines are all zeros Flag...

Страница 160: ...uring the I O transaction the peripheral address from the instruction is placed on the address bus Any bytes of address not specified in the instruction are driven on the address lines are all zeros F...

Страница 161: ...a fixed port address The decremented B register is used in the address First the B register used as a counter is decremented by one The byte of data from the memory location addressed by the HL regist...

Страница 162: ...gister used as a counter is decremented by one The word of data from the memory location addressed by the HL register is loaded into the selected peripheral The HL register is then decremented by two...

Страница 163: ...a fixed port address The decremented B register is used in the address First the B register used as a counter is decremented by one The byte of data from the memory location addressed by the HL regist...

Страница 164: ...gister used as a counter is decremented by one The word of data from the memory location addressed by the HL register is loaded into the selected peripheral The HL register is then incremented by two...

Страница 165: ...s memory locations For this instruction the Flag register is the least significant byte followed by the Accumulator The SP is then incremented by two by four in the Long Word mode Note that in the Lon...

Страница 166: ...ded into the destination in ascending byte order from ascending address memory locations The SP is then incremented by two by four in the Long Word mode Note that when not in the Long Word mode the mo...

Страница 167: ...ssed by the Stack Pointer SP are loaded into the destination in ascending byte order from ascending address memory locations The SP is then incremented by two by four in the Long Word mode Flags S Una...

Страница 168: ...o the memory locations addressed by the SP in ascending byte order in ascending address memory locations For this instruction the Flag register is the least significant byte followed by the Accumulato...

Страница 169: ...end The Stack Pointer SP is decremented by two by four in Long Word mode and the source is loaded into the memory locations addressed by the SP in ascending byte order in ascending address memory loca...

Страница 170: ...rc 15 8 end The Stack Pointer SP is decremented by two by four in Long Word mode and the source is loaded into the memory locations addressed by the SP in ascending byte order in ascending address mem...

Страница 171: ...our in Long Word mode and the source is loaded into the memory locations addressed by the SP in ascending byte order in ascending address memory locations The contents of the source are unaffected Fla...

Страница 172: ...bit field in the instruction this field contains the binary encoding for the bit number to be cleared The bit number b must be between 0 and 7 Flags S Unaffected Z Unaffected H Unaffected V Unaffected...

Страница 173: ...instructionhasbeenexecuted andthatoneormoreofthesucceedinginstructionsmayalso have been fetched for decoding before this instruction has been executed When reseting Long Word mode LW the LW bit bit 6...

Страница 174: ...ecuted otherwise a value is popped from the stack and loaded into the ProgramCounter PC therebyspecifyingthelocationofthenextinstructiontobeexecuted For an unconditional return the return is always ta...

Страница 175: ...ter SPC which holds the address of the next instruction of the previously executing procedure are loaded into the Program Counter PC Note that maskable interrupts if IEF1 is set and non maskable inter...

Страница 176: ...contents of the location addressed by the Stack Pointer SP are popped into the Program Counter PC thereby specifying the location of the next instruction to be executed A special sequence of bus tran...

Страница 177: ...at the end of a procedure entered by a nonmaskable interrupt The contents of the location addressed by the Stack Pointer SP are popped into the Program Counter PC thereby specifying the location of t...

Страница 178: ...d the Carry flag is moved to bit 0 of the destination Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if pa...

Страница 179: ...of the destination Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is even cleared...

Страница 180: ...h the Carry flag and together they are rotated left one bit position Bit 7 of the accumulator is moved to the Carry flag and the Carry flag is moved to bit 0 of the accumulator Flags S Unaffected Z Un...

Страница 181: ...eplaces the Carry flag Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is even clea...

Страница 182: ...if the most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is even cleared otherwise N Cleared C Set if th...

Страница 183: ...ents of the accumulator are rotated left one bit position Bit 7 of the accumulator is moved to the bit 0 position and also replaces the Carry flag Flags S Unaffected Z Unaffected H Cleared P Unaffecte...

Страница 184: ...er digit of the source The upper digit of the accumulator is unaffected In multiple digit BCD arithmetic this instruction can be used to shift to the left a string of BCD digits thus multiplying it by...

Страница 185: ...nd the Carry flag is moved to bit 7 of the destination Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if p...

Страница 186: ...ficant bit of the destination Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is ev...

Страница 187: ...h the Carry flag and together they are rotated right one bit position Bit 0 of the accumulator is moved to the Carry flag and the Carry flag is moved to bit 7 of the accumulator Flags S Unaffected Z U...

Страница 188: ...replaces the Carry flag Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is even cle...

Страница 189: ...s S Set if the most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is even cleared otherwise N Cleared C S...

Страница 190: ...ents of the accumulator are rotated right one bit position Bit 0 of the accumulator is moved to the bit 7 position and also replaces the Carry flag Flags S Unaffected Z Unaffected H Cleared P Unaffect...

Страница 191: ...pper digit of the source The upper digit of the accumulator is unaffected In multiple digit BCD arithmetic this instruction can be used to shift to the right a string of BCD digits thus dividing it by...

Страница 192: ...all to one of eight fixed locations as shown in the table below The table also indicates the encoding of the address used in the instruction encoding The address is in hexadecimal the encoding in bina...

Страница 193: ...leared otherwise H Set if there is a borrow from bit 4 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the operands are of different signs and the result is of the same...

Страница 194: ...Set if the result is negative cleared otherwise Z Set if the result is zero cleared otherwise H Set if there is a borrow from bit 12 of the result cleared otherwise V Set if arithmetic overflow occur...

Страница 195: ...is zero cleared otherwise H Set if there is a borrow from bit 12 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the operands are of different signs and the result is o...

Страница 196: ...C 8297 03 ZILOG SCF SET CARRY FLAG SCF Operation C 1 The Carry flag is set to 1 Flags S Unaffected Z Unaffected H Cleared V Unaffected N Cleared C Set Addressing Execute Mode Syntax Instruction Format...

Страница 197: ...t field in the instruction this field contains the binary encoding for the bit number to be set The bit number b must be between 0 and 7 Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Una...

Страница 198: ...32 bit words all word load instructions transfer 32 bits WhensettingExtendedmode XM theXMbit bit7 intheSRissetto1 selectingaddresses modulo 4 294 967 296 32 bits as opposed to addresses modulo 65536 1...

Страница 199: ...to bit 0 of the destination Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is even...

Страница 200: ...Set if the most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is even cleared otherwise N Cleared C Set...

Страница 201: ...peration to stop thus minimizing power dissipation The STNBY signal is asserted to indicate this Standby mode status STNBY remains asserted until an interrupt or reset request is accepted which causes...

Страница 202: ...lag and bit 7 remains unchanged Flags S Set if the result is negative cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is even cleared otherwise...

Страница 203: ...anged Flags S Set if the result is negative cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is even cleared otherwise N Cleared C Set if the bit...

Страница 204: ...rry flag and zero is shifted into bit 7 of the destination Flags S Cleared Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is even cleared otherwise N Cleared C S...

Страница 205: ...gnificant bit of the destination Flags S Cleared Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is even cleared otherwise N Cleared C Set if the bit shifted from...

Страница 206: ...t if there is a borrow from bit 4 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the operands are of different signs and the result is of the same sign as the source cl...

Страница 207: ...complement subtraction is performed Note that the length of the operand is controlled by the Extended Native mode selection which is consistent with the manipulation of an address by the instruction...

Страница 208: ...ce is stored in the SP register This has the effect of allocating or deallocating space on the stack Two s complement subtraction is performed Flags S Unaffected Z Unaffected H Set if there is a borro...

Страница 209: ...rwise H Set if there is a borrow from bit 12 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the operands are of different signs and the result is of the same sign as th...

Страница 210: ...ficant word of the source are exchanged with the contents of the least significant word of the source Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Exe...

Страница 211: ...ed only the flags are modified as a result of this instruction Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if all bits of the result are zero cleared otherwise...

Страница 212: ...ll be generated as a result of this instruction although the I O address will appear on the adress bus while the internal read is occurring The peripheral address in the C register is placed on the lo...

Страница 213: ...wise a 0 bit is stored The contents of the source are unaffected Flags S Set if the most significant bit of the result is set cleared otherwise Z Set if all bits of the result are zero cleared otherwi...

Страница 214: ...tomer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in...

Страница 215: ...NMI is reserved for high priority external events that need imme diateattention suchasanimminentpowerfailure Maskable Interrupts are Interrupts that can be disabled masked through software by cleaning...

Страница 216: ...U provides an Interrupt Register Extension whose contents are always output as the address bus signals A31 A16 when fetching the starting addresses of service routines from memory in Interrupt Modes 2...

Страница 217: ...vice routine Z80 I O device RET NC NC Returns from service routine or returns from Interrupt service routine for a non Z80 I O device EI 1 1 DI 0 0 LD A I or LD R I NC NC IEF2 value is copied to P V F...

Страница 218: ...to increase software reliability or to implement extended instructions An undefined opcode can be fetched from the instruction stream or it can be returned as a vector in an Interrupt acknowledge tra...

Страница 219: ...a bus contents are ignored by theZ380MPU TheinterruptedPCvalueispushedontothe stack The size of the PC value pushed onto the stack is depends on Native one word or Extended mode two words in effect Th...

Страница 220: ...onto both portions of the data bus D15 D8 and D7 D0 in the transactions Regardless of the Interrupt Mode in effect interrupts on INT3 INT1 is always handled by the Assigned Interrupt Mode This mode i...

Страница 221: ...6 Internet http www zilog com 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of...

Страница 222: ...LK input must be stable for more than five cycles with RESET held Low The Z380 CPU proceeds to fetch the first instruction 3 5 BUSCLK cycles after RESET is deasserted provided such deassertion meets t...

Страница 223: ...lected AF Main Bank IX IY Native Mode Maskable Interrupts Disabled in Mode 0 Bus Request Lock Off A and F Registers Register Banks 3 0 A F A F Unaffected Register Extensions 0000 Register Bank 0 BCz D...

Страница 224: ...http www zilog com 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc...

Страница 225: ...ormat 2 is for instructions with an opcode escape byte Format 3 is for instructions whose opcode escape byte has the value 0CBH and Format 4 is for instructions whose escape bytes are 0ED followed by...

Страница 226: ...code 1 byte Displacement LD A IX d DD 7E disp A esc Opcode Immediate LD IX nn DD 21 n L n H A esc Opcode 1 byte Displacement Immediate LD IY d n FD 36 d n Note A esc is an addressing mode escape byte...

Страница 227: ...http www zilog com 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc...

Страница 228: ...iateDecoderDirectives Extended mode orNativemode ofoperation and WordorLong Word mode of operation I means the instruction can be used with DDIR IM to expand its immediate constant X means that the op...

Страница 229: ...IYL FD 85 ADD A IYU FD 84 ADD A L 85 ADD HL 1234H I X ED C6 34 12 ADD HL BC X 09 ADD HL DE X 19 ADD HL HL X 29 Source Code Mode Object Code ADD HL SP X 39 ADD IX BC X DD 09 ADD IX DE X DD 19 ADD IX I...

Страница 230: ...3 IX 12H I DD CB 12 5E BIT 3 IY 12H I FD CB 12 5E BIT 3 A CB 5F BIT 3 B CB 58 BIT 3 C CB 59 Source Code Mode Object Code BIT 3 D CB 5A BIT 3 E CB 5B BIT 3 H CB 5C BIT 3 L CB 5D BIT 4 HL CB 66 BIT 4 I...

Страница 231: ...CP IY 12H I FD BE 12 CP 12H FE 12 CP A BF CP A HL BE CP A IX 12H I DD BE 12 CP A IY 12H I FD BE 12 CP A 12H FE 12 CP A A BF CP A B B8 CP A C B9 CP A D BA CP A E BB CP A H BC CP A IXL DD BD CP A IXU DD...

Страница 232: ...EX A A ED 3F EX A A CB 37 EX A B ED 07 EX A C ED 0F EX A D ED 17 EX A E ED 1F EX A H ED 27 EX A L ED 2F EX AF AF 08 EX B B CB 30 Source Code Mode Object Code EX BC BC L ED CB 30 EX BC DE L ED 05 EX BC...

Страница 233: ...12 Source Code Mode Object Code JR C 12H X 38 12 JR NC 123456H X FD 30 56 34 12 JR NC 1234H X DD 30 34 12 JR NC 12H X 30 12 JR NZ 123456H X FD 20 56 34 12 JR NZ 1234H X DD 20 34 12 JR NZ 12H X 20 12 J...

Страница 234: ...06 12 LD B A 47 LD B B 40 LD B C 41 LD B D 42 LD B E 43 LD B H 44 LD B IXL DD 45 LD B IXU DD 44 LD B IYL FD 45 LD B IYU FD 44 LD B L 45 Source Code Mode Object Code LD BC 1234H I L ED 4B 34 12 LD BC...

Страница 235: ...D IX IY 12H I L FD CB 12 23 LD IX SP 12H I L DD CB 12 21 LD IX 1234H I L DD 21 34 12 LD IX BC L DD 07 LD IX DE L DD 17 Source Code Mode Object Code LD IX HL L DD 37 LD IX IY L DD 27 LD IXL 12H DD 2E 1...

Страница 236: ...IY 12H I FD CB 12 9A MULTUW HL 1234H ED CB 9F MULTUW HL BC ED CB 98 MULTUW HL DE ED CB 99 MULTUW HL HL ED CB 9B MULTUW HL IX ED CB 9C MULTUW HL IY ED CB 9D MULTUW IX ED CB 9C MULTUW IY ED CB 9D Source...

Страница 237: ...POP DE L D1 POP HL L E1 POP IX L DD E1 POP IY L FD E1 POP SR L ED C1 PUSH 1234H I L FD F5 34 12 Source Code Mode Object Code PUSH AF L F5 PUSH BC L C5 PUSH DE L D5 PUSH HL L E5 PUSH IX L DD E5 PUSH I...

Страница 238: ...X E8 RET Z X C8 RET X C9 RETI X ED 4D RETN X ED 45 RL HL CB 16 RL IX 12H I DD CB 12 16 RL IY 12H I FD CB 12 16 Source Code Mode Object Code RL A CB 17 RL B CB 10 RL C CB 11 RL D CB 12 RL E CB 13 RL H...

Страница 239: ...4H ED 9E 34 12 SBCW BC ED 9C SBCW DE ED 9D SBCW HL ED 9F SBCW HL IX 12H DD DE 12 Source Code Mode Object Code SBCW HL IY 12H FD DE 12 SBCW HL 1234H ED 9E 34 12 SBCW HL BC ED 9C SBCW HL DE ED 9D SBCW H...

Страница 240: ...SLA L CB 25 SLAW HL ED CB 22 SLAW IX 12H I DD CB 12 22 SLAW IY 12H I FD CB 12 22 SLAW BC ED CB 20 SLAW DE ED CB 21 Source Code Mode Object Code SLAW HL ED CB 23 SLAW IX ED CB 24 SLAW IY ED CB 25 SLP...

Страница 241: ...ED 1C TST H ED 24 TST L ED 2C TSTIO 12H ED 74 12 XOR HL AE XOR IX 12H I DD AE 12 XOR IY 12H I FD AE 12 XOR 12H EE 12 XOR A AF XOR A HL AE XOR A IX 12H I DD AE 12 XOR A IY 12H I FD AE 12 XOR A 12H EE...

Страница 242: ...http www zilog com 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc...

Страница 243: ...Extended mode orNativemode ofoperation and WordorLong Word Mode of operation I means the instruction can be used with DDIR IM to expand its immediate constant X means that the operation of the instruc...

Страница 244: ...EC H 26 12 LD H 12H 27 DAA 28 12 JR Z 12H X 29 ADD HL HL X 2A 34 12 LD HL 1234H I L 2B DEC HL X 2B DECW HL X 2C INC L 2D DEC L 2E 12 LD L 12H 2F CPL A Object Code Source Code Mode 2F CPL 30 12 JR NC 1...

Страница 245: ...C A L 8E ADC A HL 8F ADC A A 90 SUB A B 91 SUB A C 92 SUB A D 93 SUB A E 94 SUB A H 95 SUB A L 96 SUB A HL 97 SUB A A 98 SBC A B Object Code Source Code Mode 99 SBC A C 9A SBC A D 9B SBC A E 9C SBC A...

Страница 246: ...B 12 RL D CB 13 RL E CB 14 RL H CB 15 RL L CB 16 RL HL CB 17 RL A CB 18 RR B CB 19 RR C Object Code Source Code Mode CB 1A RR D CB 1B RR E CB 1C RR H CB 1D RR L CB 1E RR HL CB 1F RR A CB 20 SLA B CB 2...

Страница 247: ...7F BIT 7 A CB 80 RES 0 B CB 81 RES 0 C CB 82 RES 0 D CB 83 RES 0 E CB 84 RES 0 H CB 85 RES 0 L CB 86 RES 0 HL Object Code Source Code Mode CB 87 RES 0 A CB 88 RES 1 B CB 89 RES 1 C CB 8A RES 1 D CB 8...

Страница 248: ...F1 SET 6 C CB F2 SET 6 D Object Code Source Code Mode CB F3 SET 6 E CB F4 SET 6 H CB F5 SET 6 L CB F6 SET 6 HL CB F7 SET 6 A CB F8 SET 7 B CB F9 SET 7 C CB FA SET 7 D CB FB SET 7 E CB FC SET 7 H CB F...

Страница 249: ...L DD 5D LD E IXL DD 5D LD E IYL DD 5E 12 LD E IX 12H I DD 60 LD IXU B DD 61 LD IXU C DD 62 LD IXU D Object Code Source Code Mode DD 63 LD IXU E DD 64 LD IXU IXU DD 65 LD IXU IXL DD 66 12 LD H IX 12H...

Страница 250: ...de Source Code Mode DD CB 12 2B LD IX 12H IY I L DD CB 12 2E SRA IX 12H I DD CB 12 31 LD HL SP 12H I L DD CB 12 33 LD HL IX 12H I L DD CB 12 39 LD SP 12H HL I L DD CB 12 3A SRLW IX 12H I DD CB 12 3B L...

Страница 251: ...2H B ED 02 LD BC BC L ED 03 EX BC IX L ED 04 TST B ED 05 EX BC DE L ED 06 34 12 LDW BC 1234H I L ED 07 EX A B ED 08 12 IN0 C 12H ED 09 12 OUT0 12H C ED 0B EX BC IY L ED 0C TST C ED 0D EX BC HL L ED 0E...

Страница 252: ...6 34 12 ADDW HL 1234H ED 87 ADDW HL ED 87 ADDW HL HL ED 8B OTDM ED 8C ADCW BC ED 8C ADCW HL BC ED 8D ADCW DE Object Code Source Code Mode ED 8D ADCW HL DE ED 8E 34 12 ADCW 1234H ED 8E 34 12 ADCW HL 12...

Страница 253: ...ED CB 20 SLAW BC ED CB 21 SLAW DE ED CB 22 SLAW HL ED CB 23 SLAW HL ED CB 24 SLAW IX ED CB 25 SLAW IY Object Code Source Code Mode ED CB 28 SRAW BC ED CB 29 SRAW DE ED CB 2A SRAW HL ED CB 2B SRAW HL E...

Страница 254: ...RET S X F9 LD SP HL L FA 34 12 JP M 1234H I X Object Code Source Code Mode FA 34 12 JP S 1234H I X FB EI FC 34 12 CALL S M 1234H I X FD 01 LD BC IY L FD 02 LD BC HL L FD 03 LD IY BC L FD 07 LD IY BC...

Страница 255: ...HL IY FD 8F ADCW IY FD 94 SUB A IYU FD 95 SUB A IYL FD 96 12 SUB A IY 12H I FD 97 SUBW HL IY Object Code Source Code Mode FD 97 SUBW IY FD 9C SBC A IYU FD 9D SBC A IYL FD 9E 12 SBC A IY 12H I FD 9F SB...

Страница 256: ...IVUW IY 12H I FD CB 12 BA DIVUW HL IY 12H I FD CB 12 BE RES 7 IY 12H I FD CB 12 C6 SET 0 IY 12H I FD CB 12 CE SET 1 IY 12H I FD CB 12 D6 SET 2 IY 12H I FD CB 12 DE SET 3 IY 12H I FD CB 12 E6 SET 4 IY...

Страница 257: ...http www zilog com 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc...

Страница 258: ...able in the Appendix B The Table D 1 has the instructions which works differently in the Native and Extended mode of operation and the Table D 2 has the instructions which works differently in Word Lo...

Страница 259: ...ALR PO 123456H FD E4 56 34 12 CALR PO 1234H DD E4 34 12 CALR PO 12H ED E4 12 CALR Z 123456H FD CC 56 34 12 CALR Z 1234H DD CC 34 12 CALR Z 12H ED CC 12 CPD ED A9 CPDR ED B9 CPI ED A1 CPIR ED B1 DEC BC...

Страница 260: ...E BC FD 0D LD DE DE FD 1D LD DE HL FD 3D LD DE IX DD 11 LD DE IY FD 11 LD HL BC FD 0F LD HL DE FD 1F LD HL HL FD 3F LD HL IX DD 31 LD HL IY FD 31 LD BC BC DD 0C LD BC DE DD 0D LD BC HL DD 0F LD BC BC...

Страница 261: ...gnificant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com 1994 1995 1996 1997 by Zilog...

Страница 262: ...P 123456H ED 92 56 34 12 Table E 2 Valid with DDIR IB XM bit status does not affect the operation Transfer size determined by LW bit Either with DDIR IB DDIR IB LW or DDIR IB W LD 123456H BC ED 43 56...

Страница 263: ...7 IY 1234H FD CB 34 12 7E CP IX 1234H DD BE 34 12 CP IY 1234H FD BE 34 12 CP A IX 1234H DD BE 34 12 CP A IY 1234H FD BE 34 12 CPW IX 1234H DD FE 34 12 CPW IY 1234H FD FE 34 12 CPW HL IX 1234H DD FE 3...

Страница 264: ...CB 34 12 0A RRW IX 1234H DD CB 34 12 1A RRW IY 1234H FD CB 34 12 1A SBC A IX 1234H DD 9E 34 12 SBC A IY 1234H FD 9E 34 12 SBCW IX 1234H DD DE 34 12 SBCW IY 1234H FD DE 34 12 SET 0 IX 1234H DD CB 34 1...

Страница 265: ...ED 63 78 56 34 12 LD 12345678H IX DD 22 78 56 34 12 LD 12345678H IY FD 22 78 56 34 12 LD 12345678H SP ED 73 78 56 34 12 LD IX 123456H BC DD CB 56 34 12 0B LD IX 123456H DE DD CB 56 34 12 1B LD IX 1234...

Страница 266: ...2 CP IY 123456H FD BE 56 34 12 CP A IX 123456H DD BE 56 34 12 CP A IY 123456H FD BE 56 34 12 CPW IX 123456H DD FE 56 34 12 CPW IY 123456H FD FE 56 34 12 CPW HL IX 123456H DD FE 56 34 12 CPW HL IY 1234...

Страница 267: ...123456H DD CB 56 34 12 86 RES 0 IY 123456H FD CB 56 34 12 86 RES 1 IX 123456H DD CB 56 34 12 8E RES 1 IY 123456H FD CB 56 34 12 8E RES 2 IX 123456H DD CB 56 34 12 96 RES 2 IY 123456H FD CB 56 34 12 9...

Страница 268: ...http www zilog com 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc...

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