ZiLOG Z80380, Руководство пользователя

Страница: 216 / 268

6-2
Z380
™
U
SER
'
S
M
ANUAL
DC-8297-03
Z
ILOG
6.2 INTERRUPTS (Continued)
In an Interrupt acknowledge transaction, address outputs
A31-A4 are driven to logic 1. One output among A3-A0 is
driven to logic 0 to indicate the maskable interrupt request
being acknowledged. If /INT0 is being acknowledged, A3-
A1 are at logic 1 and A0 is at logic 0.
For the maskable Interrupt on /INT0 input, Interrupt Modes
0 through 3 are supported. Modes 0, 1, and 2 have the
same schemes as those in the Z80 and Z180 MPU’s. Mode
3 is similar to mode 2, except that 16-bit Interrupt vectors
are expected from the I/O devices. Note that 8-bit and 16-
bit I/O devices can be intermixed in this mode by having
external pull-up resistors at the data bus signals D15-D8,
for example.
The external maskable Interrupt requests /INT3-/INT1 are
always handled in an assigned Interrupt vectors mode
regardless of the current Interrupt Mode (IM3-IM0) in
effect.
As discussed in the CPU Architecture section, the Z380
MPU can operate in either the Native or Extended mode.
In Native mode, pushing and popping of the stack to save
and retrieve interrupted PC values in Interrupt handling are
done in 16-bit sizes, and the Stack Pointer rolls over at the
64 Kbyte boundary. In Extended mode, the PC pushes and
pops are done in 32-bit sizes, and the Stack Pointer rolls
over at the 4 Gbyte memory space boundary. The Z380
MPU provides an Interrupt Register Extension, whose
contents are always output as the address bus signals
A31-A16 when fetching the starting addresses of service
routines from memory in Interrupt Modes 2, 3, and the
assigned vectors mode. In Native mode, such fetches are
automatically done in 16-bit sizes and in Extended mode,
in 32-bit sizes. These starting addresses should be even-
aligned in memory locations. That is, their least significant
bytes should have addresses with A0 = 0.
6.2.1 Interrupt Priority Ranking
The Z380 MPU assigns a fixed priority ranking to handle its
Interrupt sources, as shown in Table 6-1.
Table 6-1. Interrupt Priority Ranking
Priority Interrupt Sources
Highest Trap (undefined opcode)
/NMI
/INT0
/INT1
/INT2
Lowest /INT3
6.2.2 Interrupt Control
The Z380 MPU’s flags and registers associated with Inter-
rupt processing are listed in Table 6-2. As discussed in the
Chapter 1, “CPU Architecture,” some of these registers reside in the on-chip I/O address space, and can be
accessed only with reserved on-chip I/O instructions.
Table 6-2. Interrupt Flags and Registers
Names Mnemonics Access Methods
Interrupt Enable Flags IEF1,IEF2 EI and DI Instructions
Interrupt Register I LD I,A and LD A,I Instructions
Interrupt Register Extension Iz LD I,HL and LD HL,I Instructions
(Accessing both Iz and I)
Interrupt Enable Register IER On-chip I/O Instructions, Address 17H
EI and DI Instruction
Assigned Vectors Base and Trap Register AVBR On-Chip I/O Instructions, Address 18H
Trap and Break Register TRPBK On-Chip I/O Instructions, Address 19H