10. Parallel I/O
92
7
6
5
4
3
2
1
0
Bank Bank
1
0
0
0
0
Port Port Port
2
1
0
Port Write Inhibit
0 Inactive
1 Active
Bank Address
00 Bank 0
01 Bank 1
10 Bank 2
11 Undefined
Register: Write Inhibit/Bank Address
Mode: Enhanced (Bank 0)
Address: 7Fh
Access: Read and Write
Write Inhibit /Bank Address Register
Note:
A 11b is an invalid state and should never be written to the Mask Register.
7
6
5
4
3
2
1
0
Register: Port 0,1, and 2 Event Sense (Read)
Mode: Enhanced (Bank 1)
Address: 78-7Ah
Access: Read and Write
Event Sense Status
0 Inactive
1 Active
Bit7 Bit 6 Bit 5 Bit 4 Bit 3
7
6
5
4
3
2
1
0
Bit 2 Bit 1 Bit 0
Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register: Port 0,1, and 2 Event Sense (Write)
Mode: Enhanced (Bank 1)
Address: 78-7Ah
Access: Read and Write
Event Sense Control
0 Clear
1 Re-arms Event Input
Port Event Sense Register
