3. STD Bus Interface
24
STD 32 BUS COMPATIBILITY
The ZT 8904 is compatible with Revision 1.2 of the
STD 32 Bus Specification (Ziatech
part number ZT MSTD32). Optional STD 32 features are discussed in terms of
compliance levels.
•
Permanent Master: SA16, SA8 - I, SDMABP, {MD}
•
Temporary Master: SA16, SA8 - I, SDMABP, {MD}
Compliance Levels
The following is a brief description of the STD 32 compliance levels supported by the
ZT 8904.
SA16, SA8
Supports 8-bit and 16-bit data transfers with STD-80 signal format and
timings. The ZT 8904 automatically determines the width of the data
transfer at the start of each STD bus operation. STD-80 compatible
memory and I/O boards are supported.
I
Supports four additional STD bus interrupts: INTRQ1*, INTRQ2*,
INTRQ3*, and INTRQ4*. These interrupts are input from the STD bus and
connected to the interrupt controller through a jumper configuration block
for increased flexibility.
SDMABP
Supports Standard Architecture DMA using BUSRQ*/BUSAK* for request
and acknowledge and the backplane DMA control signals DMAIOR*,
DMAIOW*, and T-C. It is not permissible to program the DMA controller
for cascaded operation.
{MD}
Supports the multiple master (DREQx*, DAKx*) protocol. These two
signals are used by the ZT 8904 in a multiple master architecture to gain
control of STD bus resources. The use of these signals requires a bus
arbiter, such as the ZT 89CT39, to be plugged into Sot X.
STD BUS INTERRUPTS
The ZT 8904 supports both maskable and non-maskable interrupts from the STD bus.
This section discusses system level issues related to these interrupts. Refer to
Chapter 4, "
Interrupt Controller
," for more information on the maskable interrupt
controllers.
