© Copyright 2013 Zephyr Engineering, Inc
UDPSDR-
HF1 User’s Manual
20
Version 1.1
– 16 September 2013
AUD IO D AC
ADC
0dB
20dB
14b@ 80MS PS
ADC
ADC
D RI VER
ANTI ALI AS
FI LTER
LOW-PASS
FI LTER
EXTERN AL
ANTENN A
30 MH z
5kH z
14
P
H
O
N
E
S
B
e
M
ic
ro
S
D
K
(
8
0
p
in
s
)
C LK IN
C LK OU T
SEL OSC
14b@ 50KS PS
SER IAL D AC
H EAD PHON E
D RI VER
R ECONSTR UC TI ON
FI LTER
PW R
ESD
PR OT
30 MH z
UDPSDR- HF1
14 bits @ 80 M SPS
80MHz
Figure 10 - UDPSDR-HF1 Hardware Block Diagram
5.2 UPDSDR-HF1 FPGA Code
The UDPSDR-HF1 simplified FPGA block diagram is shown in Figure 11. This very
basic flow shows the Numerically Controlled Oscillator and the two multipliers that serve
as a down-converter, followed by two decimating filters. The I/Q data is buffered by a
FIFO and sent to the Ethernet MAC for transmission as UDP packets on the network.
UDPSDR- HF1
14 bits @ 80 M SPS
1.25 M Hz RF
Bandw idth
50
N CO
14
C IC
LPF
16
90
0
16
30
30
N IOS I I
ADC
10/ 100 MAC
FI FO
32Mx16
MDD R
D RAM
BeM icro EP4CE22 FPGA
4
10/ 100 PHY
D EC
FR EQ
Q
I
U SER
FLASH
B LOC K
Figure 11 - UDPSDR-HF1 Simplified FPGA Firmware Block Diagram
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