Yamaha RX-V3900, Руководство по обслуживанию

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91
RX-V3900/DSP-AX3900
RX-V390
0/
DSP-AX390
0
Pin
No.
Port Name
Function
Name
(P.C.B.)
I/O
Detail of Function
P
o
w
er On
Standb
y
MCU Sleep [A
C OFF]
CEC Standb
y [OFF]
Sleep
1 TXD4 SIRTXD
SO O O Asynchronous data output for SIRIUS (U, C models)
O O O
Hardware connection is NC / Perform Low Fix treatment also when power on
(R, T, K, A, B, G, E, L, J models)
2 P9_5 SCKN
O O O Clock output for FL DRIVER IC / PT6302
O O O Clock output for EPROM IC / BR25L320F-W
O O O
Clock output for expanded IC / LC709004A
Max. 2MHz when using VDD=4.5 to 6V
3 P9-4 PRI I O O Current protection detection / 100k pull-down
4 DA1 LMTCNT DA O O Limiter control output
5 SDA3
– O O O
Hardware connection is NC / Perform Low Fix treatment also when power on
(U, C, R, T, K, A, B, G, E, L models)
SDACEC SIO SIO O
CEC microprocessor I2C_SDA port (open drain input/output)
Set to “Low Fix” when 4.7k pull-up and CEC_PE=Low (ES only)
Set to “L” before [CEC_PE, VPOWER]=[0, 0] and to “H” after [CEC_PE,
VPOWER]≠[0, 0] (J model)
6 SCL3
– O O O
Hardware connection is NC / Perform Low Fix treatment also when power on
(U, C, R, T, K, A, B, G, E, L models)
SCLCEC SIO SIO O
CEC microprocessor I2C_SCL port (open drain input/output)
Set to “Low Fix” when 4.7k pull-up and CEC_PE=Low (ES only)
Set to “L” before [CEC_PE, VPOWER]=[0, 0] and to “H” after [CEC_PE,
VPOWER]≠[0, 0] (J model)
7 TB0in /VSYNC TMR O O Vertical sync pulse INT
8 P146
RSELDT0 O O O
Recout SW1 control (ROHM) data
Clock speed: 20us, MSBF
(U, C, R, T, K, A, B, G, E, L models)
– O O O
Hardware connection is NC because J model has no Zone 2, 3
Perform Low Fix treatment also when power on (J model)
9 P145
RSELCK0 O O O Recout SW1 control (ROHM) clock (U, C, R, T, K, A, B, G, E, L models)
– O O O
Hardware connection is NC because J model has no Zone 2, 3
Perform Low Fix treatment also when power on (J model)
10 P144 ISELDT0 O O O Recout SW1 control (ROHM) data / Clock speed: 20us, MSBF
11 P143 ISELCK0 O O O Recout SW1 control (ROHM) clock
12 INPC1_6 HDIMT IRQ O O HDMI MUTE input
13 P141 /CSDAC1 O O O Chip enable of 2shDAC (PCM1791A) *6
14 P140
– O O O
Hardware connection is NC / Perform Low Fix treatment also when power on
(U, C, R, T, K, A, B, G, E, L models)
/INTCEC
TMR
[O]
O
CEC command processing request interrupt input / 10k pull-up
CEC_PUPWR (Pin113@M32C)=Hi-Z -> Low Fix (OUT) (J model)
15 BYTE BYTE MCU MCU MCU MCU External data bus width change: 16bit
16 CNVss CNVss MCU MCU MCU MCU
Processor mode selection: Single chip mode / Hi: To flash built-in boot mode
To boot mode with P50=H, P55=L, CNVss=H setting when resetting the hardware
17 P87 /ICD O O O DIR initial clear
18 P86 /CSTI I O O TI #1 SPI READY
19 RESET RESET MCU MCU MCU MCU
20 Xout Xout MCU MCU MCU MCU
21 Vss Vss MCU MCU MCU MCU
22 Xin Xin MCU MCU MCU MCU
23 Vcc Vcc MCU MCU MCU MCU
24 NMI NMI IRQ I I
25 INT2 REM2
IRQ IRQ
IRQ
[O]
Remote control pulse input 2 / Remote control pulse input for Zone
(U, C, R, T, K, A, B, G, E, L models)
O O O
Hardware connection is NC
Perform Low Fix treatment also when power on because there is no remote
control input for Zone
Perform Low Fix treatment also when power on (J model)
26 INT1 PDET IRQ IRQ IRQ Power detection / 100k pull-up to 5M2 on SUB TR P.C.B.
27 INT0 RXDR IRQ IRQ
IRQ
[O]
RS232C · YDC reception detection
28 TA4in iPDET TMR O O iPod detection
29 RXD5
HDRXD SI O O Asynchronous data input for HD-Radio (U model)
PLLR I O O
PLL reception for tuner / Reception clock 20us / LSB fast
(C, A models)
– O O O
Hardware connection is NC / Perform Low Fix treatment also when power on
(R, T, K, B, G, E, L, J models)