Yamaha RX-V3900, Руководство по обслуживанию

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102
RX-V3900/DSP-AX3900
RX-V390
0/
DSP-AX390
0
Pin No. Port Name Function Name (P.C.B.) I/O Detail of Function
54 VDD MCU
55 VSS MCU
56 PIO[27] MON_N_VMT_3 O
Video monitor signal mute
L: Mute on / H: Mute off
57 TXD1 –
58 RXD1 –
59 PI5_XCTS1 –
60 PO5_XRTS1 –
61 PIO[9] HTX2_N_RST O Resetting for SII9134 #2
62 PIO[10] HRX_N_RST O Resetting for SII9135A
63 PIO[11] HEQ_N_RST_F O Resetting for SII9185A
64 PIO[12] VDEC_N_RST O Resetting for ADV7800
65 VDD MCU
66 VSS MCU
67 PIO[13] YGV_N_RST O Resetting for YGV619
68 PIO[14] VIPC_N_RST O Resetting for ABT2010
69 TXD2 –
70 RXD2 –
71 PI6_XCTS2 –
72 PO6_XRTS2 –
73 VDD MCU
74 VSS MCU
75 VCXI0 –
76 VDD MCU
77 PI2_X0IN –
78 NC MCU
79 VCXO0 –
80 PI3_X1IN –
81 VSS MCU
82 VDD MCU
83 VCXI1 –
84 VSS MCU
85 XIC DEV_N_RST MCU Hardware reset input for NPGA
86 NC
87 VCXO1 –
88 TEST0 For testing
89 CLKIN GA_24M I NPGA system clock 24.576MHz
90 VDD MCU
91 VSS MCU
92 TEST1 For testing
93 TEST2 For testing
94 PO1_XLOCK CEC_RY2 O CEC line switching control
95 XPCO –
96 PCO –
97 PO2 (AVI2S_ON) O Set to “H” when turning on power to AVIDEO
98 PO3 –
99 PO0_MCLKO CEC_RY1 O Switching control of CEC line
100 AMCKO GA_AMCKO O Master clock for audio
101 VDD MCU
102 VSS MCU
103 AHCKI 45.1584MHz PLL 45.158MHz clock input for generation of 11.2896MHz
104 A[7] SA[7] BUS HOST I/F address bus
105 A[6] SA[6] BUS HOST I/F address bus
106 A[5] SA[5] BUS HOST I/F address bus
107 A[4] SA[4] BUS HOST I/F address bus
108 VDD MCU
109 PI0_MCLKI –
110 VSS MCU
111 PI1_LRCK –
112 A[3] SA[3] BUS HOST I/F address bus
113 A[2] SA[2] BUS H HOST I/F address bus
114 A[1] SA[1] BUS H HOST I/F address bus