29
MCX-A10/MCX-SP10
MCX-A10/
MCX-SP10
81-92
78-80
41
94-97
104-107,
99-102,
73-76, 68-71,
63-66, 58-61,
53-56, 48-51
30
37
35
36
40
42
38
43
46
Pin No.
Symbol
A4-A15
A1-A3
AEN
nBE0-nBE3
D0-D31
RESET
nADS
nCYCLE
W/nR
nVLBUS
LCLK
ARDY
nSRDY
nRDYRTN
Address
Address
Address Enable
nByte Enable
Data Bus
Reset
nAddress Strobe
nCycle
Write/nREAD
NVLBus Access
Local Bus Clock
Asynchronous Ready
nSynchronous Ready
nReady Return Interrupt
Name
Buffer Type
I **
I **
I **
I **
I/O24 **
IS **
IS **
I **
IS **
I with pullup **
I **
OD16
O16
I **
Input signal. This signal is double signed by LAN91C111 to
determine access to the register of LAN91C111.
Input signal. This signal is used by LAN91C111 for selection
of the internal register.
Input signal. This signal is used for approval of double signing
of the address. The address can be double signed only when
AEN is in the low state.
Input signal. This signal is used to determine the register be-
ing accessed and the access width while accessing the reg-
ister of LAN91C111. When nDATACS is in the low state (burst
accessing), nBE0 - nBE3 are ignored because 32-bit trans-
mission is assumed.
Bidirectional signal. It is a 32-bit data bus that is used to ac-
cess the internal register of LAN91C111. The data bus has a
weak internal pullup register. It is usable for direct connection
with the system bus without external buffering. For the 16-bit
sytem, only D0-D15 are used.
Input signal. When this pin is in the high state, the controller
executes resetting of the internal system (MAC and PHY).
When this pin is in the high state, all registers are set to the
default value and the controller reads the contents of the
EEPROM device through the EEPROM interface (1). This in-
put is not considered effective unless it is active for at least
100ns for filtering of glitches.
Input signal. With the system that requires address latching,
the rising edge of nADS indicates the time of A1-A15 and
AEN latching. The internal functions of all LAN91C111 of A1-
A15 and AEN are latched if there is no n LDEV decoding.
Input signal. This active low signal is used to control the
LAN91C111 EISA burst mode synchronous bus cycle.
Input signal. This signal determines the direction of the syn-
chronous cycle. When it is in the high state, the writing cycle
is selected and when it is low, the reading cycle is selected.
Input signal. When this signal is in the low state, LAN91C111
synchronous bus interface is set for VL bus accessing. If not,
LAN91C111is set for EISA DMA burst accessing. It does not
affect the asynchronous bus interface.
Input signal. This signal is used to interface the synchronous
bus. The maximum frequency is 50MHz. With the EISA DMA
burst mode, the maximum value is 8.33MHz.
Open drain output signal. ARDY is usable for interfacing with
the asynchronous bus to expand accessing. Its rising (comple-
tion of accessing) edge is controlled by XTA 1 clock and so
asynchronous with the host CPU, that is, bus clock.
Output signal. This output is used for interfacing the synchro-
nous bus at n VLBUS=0 to expand accessing. This signal is
usually inactive and its falling edge indicates completion. This
signal is synchronous with the bus clock LCLK.
Input signal. This input is used to complete the synchronous
reading cycle. In the EISA burst mode, it is picked up at the
falling edge and the synchronous cycle continues until the
EISA burst mode is adopted in the high state.
Function
IC901 : LAN91C111-NE
Ethernet
