Yamaha DPX-530, Руководство по обслуживанию

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55
DPX-530
DPX-1200DPX-530
■
IC BLOCK DIAGRAM
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H L
L H
1Y 1A
1
3
5
9
2
4
6
8
11
13 12
10
2Y 2A
3Y 3A
4Y 4A
5Y 5A
6Y 6A
IC580 SN74LV14APW
Function Table
H: HIGH Logic Level
L: LO W Logic Level
Inpu t (S) Fun ct ion
B
0
Connected to A
B
1
Connected to A
B1
GND
B0 A
Vcc
S
H
L
1
2
3 4
5
6
IC550 NC7SB3157P6X
1
Vin 1 CTL Vin 2 NC
2 3 4
8 7 6 5
GND Vout V NC
+
CTL
H
L Vin 1
Vin 2
BIAS
BUFFER
OUTPUT
CONTROL-OUTPUT
HD/VD
CVBS/Y
27M
8bit ADC
Digital I/F
C
Cr
Sync Sep
Timing
Clamp
x 8
D/A
Clock
Gene.
42M
X`tal
reference
clock
3line
comb
3D comb
Motion
Det.
A C C
color decord
TINT adjust
Color adjust
Vertical enhance
LTI
contrast adjust
delay adjust
ITU-R656
encode
656/601
Format
IIC-BUS
SCL
SDA
ID1
S/N Dtector
CCD alice
27M
-4fsc 4M
DRAM
27M
10bit ADC
Cb
MPX
SW
32 31
6
7
94
92
90
42-50
51-74
97
2
85
10-26
76 75
IC250 NJM2233BM
IC2A0 TC90A92AFG
PCB-MAIN(1/3)
IC2H0 TAR5S33
IC2J0 TAR5S25
IC2K0 TAR5S15
5
4
1
2
3
V
IN
V
OUT
NOISE
GND
CONTROL
Function Table
OFF
ON H
L
V
OUT
CONTROL
H=HIGH Logic Level
L=LOW Logic Level