Yaesu VX-450 series, Руководство по обслуживанию

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29 VX-450 Series UHF Band Service Manual
4-3. PLL
The PLL IC consists of reference divider, main di-
vider, phase detector, charge pumps and pulse swal-
low operation. The reference frequency from TCXO
is inputted to 10 pin of PLL IC and is divided by
reference divider.
The other hand, inputted feed back signal to 17 pin
of PLL IC from VCO is divided with the dividing
ratio which becomes same frequency as the output
of reference divider. These two signals are compared
by phase detector, the phase difference pulse is gen-
erated.
The phase difference pulse and the pulse from
through the charge pumps and LPF. It becomes the
DC voltage to control the VCO.
The oscillation frequency of VCO is locked by the
control of this DC voltage.
The PLL serial data from CPU is sent with three lines
of SDO (40 pin), SCK (36 pin) and PSTB (30 pin).
The lock condition of PLL is output from the UL (18
pin) terminal and UL becomes “H” at the time of the
lock condition and becomes “L” at the time of the
unlocked condition. The CPU always watches over
the UL condition, and when it becomes “L” unlocked
condition, the CPU prohibits transmitting and receiv-
ing.
Circuit Description (Version I & K)