Yaesu VX-450 series, Руководство по обслуживанию

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26 VX-450 Series UHF Band Service Manual
Circuit Description (Version A & D)
The phase difference pulse and the pulse from
through the charge pumps and LPF. It becomes the
DC voltage to control the VCO.
The oscillation frequency of VCO is locked by the
control of this DC voltage.
The PLL serial data from CPU is sent with three lines
of SDO (40 pin), SCK (36 pin) and PSTB (30 pin).
The lock condition of PLL is output from the UL (18
pin) terminal and UL becomes “H” at the time of the
lock condition and becomes “L” at the time of the
unlocked condition. The CPU always watches over
the UL condition, and when it becomes “L” unlocked
condition, the CPU prohibits transmitting and receiv-
ing.