Xycom AHIP-370, Руководство пользователя

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Chapter Two - Installation
15
The following table outlines the changes in jumper configurations between the
AHIP-370 and AHIP6:
Table 2- 2. Changes in Jumper Configuration
AHIP6
Jumper
AHIP-370
Jumper Description Comments
J6 N/A Controls the speed of the CPU The socket370 implementation by Intel calls
for the CPU to define its own speed and not
be determined by jumpers. There are no
jumpers on the AHIP-370 for this purpose.
J1 J1 A PB reset disabled
B PB reset enabled PB refers to an external pushbutton that may
be connected through the RS-232 interface.
J2 J2 A CPU will not clear CMOS on
power up
B CPU will clear CMOS
J3 J3 A Flat panel enabled
B CRT port enabled
J4 J4 A Normal operation
B Puts H8 in program mode
J5 N/A A Normal flash boot
B Recovery flash boot See above.
J7 J7 A CPU boots from flash
B CPU boots from ROM
J18 N/A A Onboard video enabled
B Onboard video disabled The video is always enabled on the AHIP-370.
If an external VGA adapter is plugged into the
system, the BIOS will disable the onboard
chip.
N/A J8 A The asserted state will enable
the RS-485 port.
B The negated state will enable
the RS-485 port. Refers to the state of the modem control
signal selected by J9.
N/A J9 A DTR is used to control the
RS-485 port.
B RTS is used to control the
RS-485 port.
J8 and J9 function together to control the
RS485 port.
RS-485 TriState Control
On the AHIP6, the RS-485 is enabled by
asserting DTR. Two jumpers were added to
the AHIP-370 to allow either DTR or RTS to
control the RS-485 drives and determine
whether the asserted or negated state will
enable it.
J8 J10 Used to program Lattice
component. Factory use only.
NA J14, 15, 16,
17 OUT = Xycom Controller, PS/2
Mode
IN = Xycom Controller, Serial
Mode These jumpers allow the PS/2 AUX port and
interlink mouse to pass through the Xycom
controller.