Xilinx Virtex-II Pro ML324, Руководство пользователя

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Virtex-II Pro ML324 and ML325 Platform www.xilinx.com 9
UG063 (v1.2) May 30, 2006
Introduction
R
Figure 1 shows a block diagram of the board.
Figure 1: Virtex-II Pro ML32 x Platform Block Diagram
* HEADER S
RECOVERED
CLOCK S
BER
T 2 X
3
6
BER
T
3
X
3
6
LED s
GP S W s
PB S W 3
PB S W 4
DIFF CLOCK S
RIGHT ANGLE S MA
MGT MGT
O S C
S MA
O S C
S ocket
S MA
2 X 2
DIFF
O
S C
* HEADER S
RECOVERED
CLOCK S
DIFF CLOCK S
RIGHT ANGLE S MA
RIGHT ANGLE S MA
RIGHT ANGLE S MA
PROGRAM
MGT MGT
S y s tem ACE
S ol u tion
UART
RX TX
DONE
LED
INIT
LED
LED s
GP S W s
PB S W 1
PB S W 2
Power Bu s and Switche s
5V J
a
c
k
5V Br
ic
k
-or-
VCC J
a
ck
VCCO J
a
ck
AU
X
J
a
ck
J
a
ck
MGT J
a
ck
VCORE
1.5V
VCCO
2.5V
VCCA
UX
2.5V
MGT A
U
X
2.5V
VCC
3
3
.
3
V
TX T
O
P
J
a
ck
TX T
O
P
1.8V -
2.5V
RX T
O
P
J
a
ck
RX T
O
P
1.8V -
2.5V
TX BO
T J
a
ck
TX BO
T
1.8V -
2.5V
RX BO
T J
a
ck
RX BO
T
1.8V -
2.5V
UG06 3 _01_042706
Virtex-II Pro
FPGA
* HEADERS
8 in FF1517
10 in FF1704
* MGT
4 X 4 in FF1517
4 X 5 in FF1704
LAUNCH SMA
Active High Active High
128 M b
S DRAM
O S C
S MA
O S C
S ocket
S MA
2 X 2
DIFF
O
S C